The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Jun. 25, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Debaleena Nandi, Hillsboro, OR (US);

Chi-Hing Choi, Portland, OR (US);

Gilbert Dewey, Beaverton, OR (US);

Harold Kennel, Portland, OR (US);

Omair Saadat, Portland, OR (US);

Jitendra Kumar Jha, Hillsboro, OR (US);

Adedapo Oni, North Plains, OR (US);

Nazila Haratipour, Portland, OR (US);

Anand Murthy, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/23 (2025.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01); H10D 62/832 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 64/251 (2025.01); H01L 21/28 (2013.01); H01L 21/76889 (2013.01); H10D 62/832 (2025.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01);
Abstract

Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.


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