The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2024
Filed:
Apr. 18, 2023
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Shao-Kuan Lee, Kaohsiung, TW;
Cherng-Shiaw Tsai, New Taipei, TW;
Ting-Ya Lo, Hsinchu, TW;
Cheng-Chin Lee, Taipei, TW;
Chi-Lin Teng, Taichung, TW;
Kai-Fang Cheng, Taoyuan, TW;
Hsin-Yen Huang, New Taipei, TW;
Hsiao-Kang Chang, Hsinchu, TW;
Shau-Lin Shue, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
In some embodiments, the present disclosure relates to an integrated chip that includes an electrical interconnect structure, a thermal interconnect structure, and a thermal passivation layer over a substrate. The electrical interconnect structure includes interconnect vias and interconnect wires embedded within interconnect dielectric layers. The thermal interconnect structure is arranged beside the electrical interconnect structure and includes thermal vias, thermal wires, and/or thermal layers. Further, the thermal interconnect structure is embedded within the interconnect dielectric layers. The thermal passivation layer is arranged over a topmost one of the interconnect dielectric layers. The thermal interconnect structure has a higher thermal conductivity than the interconnect dielectric layers.