The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 21, 2024
Filed:
Sep. 23, 2020
Intel Corporation, Santa Clara, CA (US);
Leonard P. Guler, Hillsboro, OR (US);
Michael K. Harper, Hillsboro, OR (US);
William Hsu, Hillsboro, OR (US);
Biswajeet Guha, Hillsboro, OR (US);
Tahir Ghani, Portland, OR (US);
Niels Zussblatt, Hillsboro, OR (US);
Jeffrey Miles Tan, Hillsboro, OR (US);
Benjamin Kriegel, Portland, OR (US);
Mohit K. Haran, Hillsboro, OR (US);
Reken Patel, Portland, OR (US);
Oleg Golonzka, Beaverton, OR (US);
Mohammad Hasan, Aloha, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along sidewalls of the first gate stack, a second portion forming a gate spacer along sidewalls of the second gate stack, and a third portion completely filling the gap, the third portion continuous with the first and second portions.