The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Mar. 30, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Daniel G. Ouellette, Portland, OR (US);

Christopher J. Wiegand, Portland, OR (US);

Md Tofizur Rahman, Portland, OR (US);

Brian Maertz, Santa Barbara, CA (US);

Oleg Golonzka, Beaverton, OR (US);

Justin S. Brockman, Portland, OR (US);

Kevin P. O'Brien, Portland, OR (US);

Brian S. Doyle, Portland, OR (US);

Kaan Oguz, Beaverton, OR (US);

Tahir Ghani, Portland, OR (US);

Mark L. Doczy, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 43/02 (2006.01); H01L 43/08 (2006.01); H01L 43/12 (2006.01); H01L 27/22 (2006.01); H01L 43/10 (2006.01);
U.S. Cl.
CPC ...
H01L 43/02 (2013.01); H01L 27/222 (2013.01); H01L 43/08 (2013.01); H01L 43/10 (2013.01); H01L 43/12 (2013.01);
Abstract

Strain engineering of perpendicular magnetic tunnel junctions (PMTJs) is described. In an example, a memory structure includes a perpendicular magnetic tunnel junction (pMTJ) element disposed above a substrate. A lateral strain-inducing material layer is disposed on the pMTJ element. An inter-layer dielectric (ILD) layer disposed laterally adjacent to both the pMTJ element and the lateral strain-inducing material layer.


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