The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2020
Filed:
Jan. 18, 2019
United Microelectronics Corp., Hsin-Chu, TW;
Kai-Lin Lee, Kinmen County, TW;
Zhi-Cheng Lee, Tainan, TW;
Wei-Jen Chen, Tainan, TW;
Ting-Hsuan Kang, Taichung, TW;
Ren-Yu He, Taichung, TW;
Hung-Wen Huang, New Taipei, TW;
Chi-Hsiao Chen, Chiayi, TW;
Hao-Hsiang Yang, Taoyuan, TW;
An-Shih Shih, Taoyuan, TW;
Chuang-Han Hsieh, Tainan, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Abstract
A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.