The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Mar. 01, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Wen Cheng, Tainan, TW;

Wei-Yip Loh, Hsinchu, TW;

Yu-Hsiang Liao, Hsinchu, TW;

Sheng-Hsuan Lin, Zhubei, TW;

Hong-Mao Lee, Hsinchu, TW;

Chun-I Tsai, Hsinchu, TW;

Ken-Yu Chang, Hsinchu, TW;

Wei-Jung Lin, Hsinchu, TW;

Chih-Wei Chang, Hsinchu, TW;

Ming-Hsing Tsai, Chu-Pei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/285 (2006.01); H01L 23/522 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/28518 (2013.01); H01L 21/4853 (2013.01); H01L 21/76831 (2013.01); H01L 21/76886 (2013.01); H01L 21/76897 (2013.01); H01L 21/823871 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/72 (2013.01); H01L 24/81 (2013.01); H01L 29/66575 (2013.01);
Abstract

A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region. Finally, a surface treatment can be performed in the contact region to form N-rich areas in the dielectric layer and a nitridation region in the substrate, and an adhesion layer can formed in the contact region to cover the side portions and the bottom portion of the contact region.


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