The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2019
Filed:
Mar. 28, 2016
Intel Corporation, Santa Clara, CA (US);
Christopher J. Wiegand, Portland, OR (US);
Oleg Golonzka, Beaverton, OR (US);
MD Tofizur Rahman, Portland, OR (US);
Brian S. Doyle, Portland, OR (US);
Mark L. Doczy, Beaverton, OR (US);
Kevin P. O'Brien, Portland, OR (US);
Kaan Oguz, Beaverton, OR (US);
Tahir Ghani, Portland, OR (US);
Satyarth Suri, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of a dielectric layer above a substrate, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.