The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Apr. 28, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Jiung Wu, Kueishan Shiang, TW;

Kuan-Liang Lai, Tainan, TW;

Ming-Tsu Chung, Hsin-Chu, TW;

Hong-Ye Shih, New Taipei, TW;

Ku-Feng Yang, Baoshan Township, TW;

Tsang-Jiuh Wu, Hsin-Chu, TW;

Wen-Chih Chiou, Zhunan Township, TW;

Shin-Puu Jeng, Hsin-Chu, TW;

Chen-Hua Yu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 21/30625 (2013.01);
Abstract

An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.


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