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For the Inventor, By the Inventor

Hsinchu, Taiwan

Yung-Liang Kuo

USPTO Granted Patents = 11

Average Co-Inventor Count = 4.5

ph-index = 3

Forward Citations = 53(Granted Patents)


Company Filing History:

goldMedal11 out of 40,635 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2009-2025

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11 patents (USPTO):
1. 12313675 - Method and device for wafer-level testing (2025-05-27),
2. 12270852 - Method and system for wafer-level testing (2025-04-08),
3. 12066484 - Method and device for wafer-level testing (2024-08-20),
4. 12025655 - Method and system for wafer-level testing (2024-07-02),
5. 11754621 - Method and device for wafer-level testing (2023-09-12),
6. 11630149 - Method and system for wafer-level testing (2023-04-18),
7. 11448692 - Method and device for wafer-level testing (2022-09-20),
8. 11073551 - Method and system for wafer-level testing (2021-07-27),
9. 8248091 - Universal array type probe card design for semiconductor device testing (2012-08-21),
10. 7781235 - Chip-probing and bumping solutions for stacked dies having through-silicon vias (2010-08-24),
11. 7598523 - Test structures for stacking dies having through-silicon vias (2009-10-06),

Title: Yung-Liang Kuo: Innovator in Semiconductor Testing

Introduction

Yung-Liang Kuo is a prominent inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of semiconductor testing, holding a total of 11 patents. His work focuses on improving the efficiency and effectiveness of testing methods for semiconductor devices.

Latest Patents

Among his latest patents is a method and device for wafer-level testing. This innovation provides a comprehensive system for testing semiconductor devices. The system includes a signal generator and a module designed to apply an initial signal to an input terminal of a device under test (DUT) during a first period, followed by a stress signal in a second period. The module is responsible for obtaining an output signal in response to both the initial and stress signals, which includes sequences with ramp-up and ramp-down stages. Notably, the duration of the first sequence is longer than that of the second sequence. This method enhances the reliability of semiconductor testing by allowing for fluctuations in voltage levels during the testing process.

Career Highlights

Yung-Liang Kuo is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His expertise in testing methodologies has positioned him as a key figure in advancing semiconductor technology.

Collaborations

He has collaborated with notable colleagues, including Jun He and Yu-Ting Lin, contributing to various projects that aim to enhance semiconductor testing processes.

Conclusion

Yung-Liang Kuo's innovative work in semiconductor testing has made a significant impact on the industry. His patents reflect a commitment to improving testing methodologies, ensuring the reliability of semiconductor devices.

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