The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Jul. 08, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Jun He, Hsinchu, TW;

Yu-Ting Lin, Hsin-Chu, TW;

Wei-Hsun Lin, Hsinchu County, TW;

Yung-Liang Kuo, Hsinchu, TW;

Yinlung Lu, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/26 (2020.01);
U.S. Cl.
CPC ...
G01R 31/2879 (2013.01); G01R 31/2642 (2013.01); G01R 31/2886 (2013.01);
Abstract

The present disclosure provides a method and a system for testing semiconductor device. The system includes a signal generator and a module. The signal generator is configured to apply an initial signal to an input terminal of a DUT during a first period; and apply a stress signal to the input terminal in a second period. The module is configured to: obtain an output signal in response to the initial signal and the stress signal at an output terminal of the DUT, the output signal in response to the stress signal including a first sequence and a second sequence, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage, wherein a duration of the first sequence is longer than that of the second sequence; and compare the output signal with the stress signal.


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