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For the Inventor, By the Inventor

Baoshan, Taiwan

Yu-Chyi Harn

This inventor holds 5 USPTO granted patents. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2003-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yu-Chyi Harn. Retrieved from https://idiyas.com/inventor/yu-chyi-harn

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 5

% Patents Active = 80.0

Average Co-Inventor Count = 2.9

ph-index = 3

Forward Citations = 74(Granted Patents)


Location History:

  • Taipei, TW (2003)
  • Hsin-Chu, TW (2013)
  • Bao-Shan, TW (2007 - 2014)

Company Filing History:

goldMedal5 out of 42,810 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2003-2014

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5 patents (USPTO):Explore Patents
1. 8786054 - Structure for integrated circuit alignment (2014-07-22),
2. 8577717 - Method and system for predicting shrinkable yield for business assessment of integrated circuit design shrink (2013-11-05),
3. 7378720 - Integrated stress relief pattern and registration structure (2008-05-27),
4. 7202550 - Integrated stress relief pattern and registration structure (2007-04-10),
5. 6517637 - Method for cleaning wafers with ionized water (2003-02-11),

Title: Yu-Chyi Harn: Innovator in Integrated Circuit Design

Introduction

Yu-Chyi Harn is a prominent inventor based in Bao-Shan, Taiwan. He has made significant contributions to the field of integrated circuit design, holding a total of 5 patents. His work focuses on enhancing the efficiency and effectiveness of integrated circuit technologies.

Latest Patents

Yu-Chyi Harn's latest patents include innovative methods and devices for pattern alignment in integrated circuits. One notable patent is a structure for integrated circuit alignment, which discloses a device that includes an exposure field, a die with an integrated circuit region, a seal ring region, and a corner stress relief region. Additionally, he has developed a method and system for predicting shrinkable yield for business assessment of integrated circuit design shrink. This system provides a cost-benefit analysis across different design shrink technologies, enabling early business decisions regarding design shrinks.

Career Highlights

Yu-Chyi Harn is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His expertise in integrated circuit design has positioned him as a valuable asset to the company.

Collaborations

Throughout his career, Yu-Chyi Harn has collaborated with notable colleagues, including Chung-Min Fu and Hsien-Wei Chen. These collaborations have furthered advancements in integrated circuit technologies.

Conclusion

Yu-Chyi Harn's contributions to integrated circuit design and his innovative patents reflect his dedication to advancing technology in the semiconductor industry. His work continues to influence the field and drive progress in integrated circuit applications.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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