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For the Inventor, By the Inventor

Hsinchu, Taiwan

Yu-Chang Lin

This inventor holds 50 USPTO granted patents and 28 published patent applications, primarily in Semiconductor Devices. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Silicon Power Computer & Communications Inc., Taiwan Semiconductor Manufacturing Co., Ltd.. Active years: 1999-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yu-Chang Lin. Retrieved from https://idiyas.com/inventor/yu-chang-lin-itwp8gnl

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 50 

% Patents Active = 80.0

Average Co-Inventor Count = 4.0

ph-index = 7

Forward Citations = 161(Granted Patents)


Location History:

  • Taipei, TW (2007 - 2010)
  • Linkou Shiang, TW (2011 - 2016)
  • Hsinchu, TW (1999 - 2024)

Company Filing History:

goldMedal44 out of 42,926 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal2 out of 9 
 
Silicon Power Computer & Communications Inc.
 patents
bronzeMedal2 out of 491 
 
Taiwan Semiconductor Manufacturing Co., Ltd.
 patents
4. 1 out of 443 
 
Mosel Vitelic Corporation
 patents
5. 1 out of 191 
 
Powerchip Semiconductor Manufacturing Corporation
 patents

Years Active: 1999-2026

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Areas of Expertise:
FinFET Structures
Ion Implantation
Channel Strain
Nanostructures
Source/Drain Regions
Thermal Annealing
Doping Techniques
3D Structure Formation
Semiconductor Manufacturing
Device Packaging
Poly-Depletion Reduction
50 patents (USPTO):Explore Patents
1. 12751078 - Doped well for semiconductor devices (2026-09-29),
2. 12707695 - Semiconductor device and method for forming the same (2026-08-11),
3. 12701760 - Semiconductor device and manufacturing method thereof (2026-08-04),
4. 12563997 - Warm wafer after ion cryo-implantation (2026-02-24),
5. 12477764 - Method of manufacturing a source/drain of a semiconductor device using multiple implantation processes (2025-11-18),
6. 12300717 - Semiconductor device and method of manufacture (2025-05-13),
7. 12255101 - Ion implantation of nanostructures for nano-FET (2025-03-18),
8. 12218196 - Semiconductor device and method of manufacture (2025-02-04),
9. 12148672 - Hybrid fin structure of semiconductor device and method of forming same (2024-11-19),
10. 12100738 - Semiconductor device with implant and method of manufacturing same (2024-09-24),
11. 12021082 - Enhanced channel strain to reduce contact resistance in NMOS FET devices (2024-06-25),
12. 11935793 - Dual dopant source/drain regions and methods of forming same (2024-03-19),
13. 11901235 - Ion implantation for nano-FET (2024-02-13),
14. 11776911 - Semiconductor device and manufacturing method thereof (2023-10-03),
15. 11670683 - Semiconductor device with implant and method of manufacturing same (2023-06-06),

Title: The Innovative Journey of Yu-Chang Lin

Introduction:

Yu-Chang Lin, a distinguished inventor hailing from Hsinchu, Taiwan, has made significant contributions to the field of technology with his groundbreaking innovations.

Latest Patents:

Yu-Chang Lin's latest patents showcase his expertise in areas such as semiconductor technology, renewable energy, and artificial intelligence, solidifying his position as a pioneer in the industry.

Career Highlights:

With a career spanning over two decades, Yu-Chang Lin has held key roles in leading tech companies, where he spearheaded research and development projects that have resulted in numerous successful patents and inventions.

Collaborations:

Throughout his career, Yu-Chang Lin has collaborated with top researchers, engineers, and scientists from around the world, fostering a culture of innovation and excellence in all his projects.

Conclusion:

In conclusion, Yu-Chang Lin's relentless pursuit of innovation and his passion for pushing the boundaries of technology have established him as a prominent figure in the world of inventions and patents.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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