Yasushi Kasatani

This inventor holds 13 USPTO granted patents. Top assignees: Mitsubishi Denki Kabushiki Kaisha, Renesas Technology Corp.. Active years: 1989-2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yasushi Kasatani. Retrieved from https://idiyas.com/inventor/yasushi-kasatani

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 13

% Patents Active = 61.5

Average Co-Inventor Count = 1.9

ph-index = 8

Forward Citations = 232(Granted Patents)

Location History:

Itami, JP (1989 - 1994)
Tokyo, JP (2002 - 2004)
Hyogo, JP (2003 - 2005)

Company Filing History:

10 out of 21,351

Mitsubishi Denki Kabushiki Kaisha

patents

3 out of 3,781

Renesas Technology Corp.

patents

Years Active: 1989-2005

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13 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6861370 - Bump formation method (2005-03-01),

2. 6798056 - Semiconductor module having an upper layer semiconductor package overlying a lower layer semiconductor package (2004-09-28),

3. 6717275 - Semiconductor module (2004-04-06),

4. 6670701 - Semiconductor module and electronic component (2003-12-30),

5. 6617695 - Semiconductor device and semiconductor module using the same (2003-09-09),

6. 6590286 - Land grid array semiconductor device (2003-07-08),

7. 6492714 - Semiconductor device and semiconductor module (2002-12-10),

8. 5363274 - Memory card (1994-11-08),

9. 5306541 - Printed circuit board and terminal board with staggered conductive pads (1994-04-26),

10. 5024605 - Connecting electrode (1991-06-18),

11. 4868714 - IC card including enclosed sliding shutter (1989-09-19),

12. 4864116 - Mechanism for connecting an IC card to an external device (1989-09-05),

13. 4838804 - Mechanism for connecting IC card and external device (1989-06-13),

Title: Yasushi Kasatani: Innovator in Semiconductor Technology

Introduction

Yasushi Kasatani is a prominent inventor based in Hyogo, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 13 patents. His innovative work has enhanced the reliability and efficiency of semiconductor devices.

Latest Patents

One of his latest patents is a bump formation method that improves the reliability of semiconductor devices by eliminating satellites generated by a solder jet-type nozzle. This method involves forming a bump on an electrode pad using a solder jet system that discharges molten solder drops. The process includes a coating layer formation step, a solder drop discharging step, and a coating layer removal step, ensuring that the work piece is protected during the soldering process.

Another notable patent is for a semiconductor module that features an upper layer semiconductor package overlying a lower layer semiconductor package. This design includes a substrate with a pad electrode and ensures that the pad electrodes of both packages are arranged alternately, optimizing space and functionality.

Career Highlights

Yasushi Kasatani has worked with several esteemed companies throughout his career, including Mitsubishi Electric Corporation and Renesas Technology Corporation. His experience in these organizations has allowed him to develop and refine his innovative ideas in semiconductor technology.

Collaborations

He has collaborated with notable colleagues such as Tetsuya Matsuura and Toshinobu Banjo, contributing to advancements in their shared field of expertise.

Conclusion

Yasushi Kasatani's contributions to semiconductor technology through his patents and collaborations have significantly impacted the industry. His innovative methods and designs continue to enhance the reliability and efficiency of semiconductor devices.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]