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For the Inventor, By the Inventor

Elmsford, NY, United States of America

Yaocheng Liu

This inventor holds 23 USPTO granted patents and 3 EPO patents, primarily in Semiconductor Technology. Top assignee: International Business Machines Corporation. Active years: 2007-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yaocheng Liu. Retrieved from https://idiyas.com/inventor/yaocheng-liu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 23

% Patents Active = 43.5


Average Co-Inventor Count = 3.7

ph-index = 8

Forward Citations = 362(Granted Patents)


Location History:

  • White Plains, NY (US) (2009)
  • Elmsford, NY (US) (2007 - 2015)

Company Filing History:

goldMedal23 out of 166,483 
 
International Business Machines Corporation
 patents

Years Active: 2007-2015

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Areas of Expertise:
MOSFETs
SOI FETs
Silicon Carbon
Stressed Layers
Device Regions
Gas Phase Doping
Performance Enhancement
Parasitic Capacitance
Semiconductor Structures
Dual Stressors
Laser Melting
Superdamascene Technique
23 patents (USPTO):Explore Patents
1. 9059316 - Structure and method for mobility enhanced MOSFETs with unalloyed silicide (2015-06-16),
2. 8642434 - Structure and method for mobility enhanced MOSFETS with unalloyed silicide (2014-02-04),
3. 8217423 - Structure and method for mobility enhanced MOSFETs with unalloyed silicide (2012-07-10),
4. 7932144 - Semiconductor structure and method of forming the structure (2011-04-26),
5. 7888197 - Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer (2011-02-15),
6. 7838932 - Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon (2010-11-23),
7. 7741658 - Self-aligned super stressed PFET (2010-06-22),
8. 7714358 - Semiconductor structure and method of forming the structure (2010-05-11),
9. 7709910 - Semiconductor structure for low parasitic gate capacitance (2010-05-04),
10. 7696000 - Low defect Si:C layer with retrograde carbon profile (2010-04-13),
11. 7675118 - Semiconductor structure with enhanced performance using a simplified dual stress liner configuration (2010-03-09),
12. 7667263 - Semiconductor structure including doped silicon carbon liner layer and method for fabrication thereof (2010-02-23),
13. 7655551 - Control of poly-Si depletion in CMOS via gas phase doping (2010-02-02),
14. 7632724 - Stressed SOI FET having tensile and compressive device regions (2009-12-15),
15. 7615435 - Semiconductor device and method of manufacture (2009-11-10),

Title: Yaocheng Liu: Pioneering Inventor from Elmsford, NY

Introduction: Yaocheng Liu is a distinguished inventor based in Elmsford, NY, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Yaocheng Liu holds several patents in the areas of artificial intelligence, renewable energy, and sustainable technologies, showcasing his commitment to creating solutions for a better future.

Career Highlights: With a career spanning over two decades, Yaocheng Liu has worked with leading tech companies, research institutions, and universities to develop cutting-edge technologies that have revolutionized various industries.

Collaborations: Throughout his career, Yaocheng Liu has collaborated with top scientists, engineers, and researchers from around the world, fostering a culture of innovation and excellence in all his projects.

Conclusion: Yaocheng Liu's passion for innovation and his relentless pursuit of technological advancement continue to inspire the next generation of inventors and entrepreneurs worldwide.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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