The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2010

Filed:

Aug. 21, 2007
Applicants:

Yaocheng Liu, Elmsford, NY (US);

Zhijiong Luo, Carmel, NY (US);

Huilong Zhu, Poughkeepsie, NY (US);

Inventors:

Yaocheng Liu, Elmsford, NY (US);

Zhijiong Luo, Carmel, NY (US);

Huilong Zhu, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0328 (2006.01);
U.S. Cl.
CPC ...
Abstract

The embodiments of the invention comprise a self-aligned super stressed p-type field effect transistor (PFET). More specifically, a field effect transistor comprises a channel region comprising N-doped material and a gate above the channel region. The field effect transistor also includes a source region on a first side of the channel region and a drain region on a second side of the channel region opposite the first side. The source and drain regions each comprise silicon germanium, wherein the silicon germanium has structural indicia of epitaxial growth.


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