The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2012
Filed:
Jan. 04, 2007
Yaocheng Liu, Elmsford, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Oleg Gluschenkov, Poughkeepsie, NY (US);
Judson R Holt, Wappingers Falls, NY (US);
Renee T MO, Briarcliff Manor, NY (US);
Kern Rim, Yorktown Heights, NY (US);
Yaocheng Liu, Elmsford, NY (US);
Dureseti Chidambarrao, Weston, CT (US);
Oleg Gluschenkov, Poughkeepsie, NY (US);
Judson R Holt, Wappingers Falls, NY (US);
Renee T Mo, Briarcliff Manor, NY (US);
Kern Rim, Yorktown Heights, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.