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For the Inventor, By the Inventor

Santa Clara, CA, United States of America

Yanjie Wang

This inventor holds 21 USPTO granted patents and 3 published patent applications, primarily in Non-Volatile Memory. Top assignees: Sandisk Technologies Inc., Applied Materials, Inc., Western Digital Technologies, Inc.. Active years: 2017-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yanjie Wang. Retrieved from https://idiyas.com/inventor/yanjie-wang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 21 

% Patents Active = 100.0

Average Co-Inventor Count = 3.2

ph-index = 2

Forward Citations = 34(Granted Patents)


Location History:

  • Santa Clara, CA (US) (2017 - 2024)
  • San Jose, CA (US) (2023 - 2024)

Company Filing History:

goldMedal16 out of 4,962 
 
Sandisk Technologies Inc.
 patents
silverMedal4 out of 14,482 
 
Applied Materials, Inc.
 patents
bronzeMedal1 out of 5,431 
 
Western Digital Technologies, Inc.
 patents

Years Active: 2017-2026

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Areas of Expertise:
Quad-Level Memory Cells
Dynamic Word Line Boosting
Read Clock Timing
Erase Process Tuning
NAND String Read Voltage
Power Saving Techniques
Adaptive Voltage Control
Programming Stress Reduction
Fast Read Sequence
Process Kit Design
Temperature Dependent Refresh
Selective Verify Pulses
21 patents (USPTO):Explore Patents
1. 12706152 - Full sequence program for edge word line quad-level memory cells (2026-08-11),
2. 12512158 - Dynamic word line boosting during programming of a memory device (2025-12-30),
3. 12400720 - Adaptive negative word line voltage (2025-08-26),
4. 12374379 - Temperature dependent refresh read rate (2025-07-29),
5. 12205647 - Programming techniques to reduce programming stress in a memory device (2025-01-21),
6. 12154630 - Non-volatile memory with tuning of erase process (2024-11-26),
7. 12142325 - Pre-read cycle timing shrink by SGD bias control and page and wordline control (2024-11-12),
8. 12142323 - Foggy-fine drain-side select gate re-program for on-pitch semi-circle drain side select gates (2024-11-12),
9. 12105963 - NAND string read voltage adjustment (2024-10-01),
10. 12094546 - Non-volatile memory with zone based program speed adjustment (2024-09-17),
11. 11978516 - Dynamic sense amplifier supply voltage for power and die size reduction (2024-05-07),
12. 11972805 - Non-volatile memory with narrow and shallow erase (2024-04-30),
13. 11887674 - Utilizing data pattern effect to control read clock timing and bit line kick for read time reduction (2024-01-30),
14. 11721397 - Power saving and fast read sequence for non-volatile memory (2023-08-08),
15. 11636897 - Peak current and program time optimization through loop dependent voltage ramp target and timing control (2023-04-25),

Title: Inventor Yanjie Wang: Revolutionizing Technology in Santa Clara

Introduction: Yanjie Wang is a visionary inventor based in Santa Clara, CA, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Yanjie Wang holds several patents in the areas of artificial intelligence, machine learning, and semiconductor technology, showcasing his expertise and forward-thinking approach to invention.

Career Highlights: With a career spanning over two decades, Yanjie Wang has worked with leading tech companies in Silicon Valley, driving innovation and spearheading projects that have redefined the industry standards.

Collaborations: Throughout his career, Yanjie Wang has collaborated with top researchers, engineers, and developers, fostering a culture of creativity and excellence that has led to the development of cutting-edge technologies.

Conclusion: Yanjie Wang's passion for innovation and his relentless pursuit of technological advancement continue to inspire the next generation of inventors and shape the future of the tech industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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