Sandisk Technologies Inc.

Applied Materials, Inc.

Western Digital Technologies, Inc.

Yanjie Wang

Guirong Liang

Yi Song

Xiaoyu Che

Jiahui Yuan

Sanjeev Baluja

Kalyanjit Ghosh

Kien Nai Chuc

Mayur G Kulkarni

Sungjin Kim

Jianzhi Wu

Henry Chin

Jun Wan

Tai-Yuan Tseng

Dale R Dubois

Ohwon Kwon

Kou Tei

Jia Li

Shota Murai

Hoon Cho

Yonggang Wu

Yasue Yamamoto

Runchen Fang

Mahdi Ganji

Yanzhen Wang

A storage device comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines. A controller, coupled to the non-volatile memory, configured to: determine, based on a stage of a product lifetime of the non-volatile memory, a negative word line setting for implementing during performance of a first operation; perform the first operation, the first operation including adjusting, based on the negative word line setting, a negative word line relative parameter; determine, based on another stage of the product lifetime of the non-volatile memory, another negative word line setting for implementing during performance of a second operation; and perform the second operation, the second operation including adjusting, based on the other negative word line setting, another negative word line relative parameter.

Adaptive negative word line voltage

Systems and methods for effecting a temperature dependent refresh read rate of a read operation of a block or sub-block of memory cells in a NAND string. The method includes initiating a refresh read cycle, determining a current temperature of the non-volatile memory device, and determining a refresh read rate corresponding to the current temperature. The refresh read is performed. The method further includes implementing a delay of a defined time period after the refresh read is performed, wherein the defined time period is based on the determined refresh read rate. If a new command is received before the delay has ended then the new command is performed, and if the delay has ended without a new command having been received then the method returns to the step of determining the current temperature.

Temperature dependent refresh read rate

The memory device includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is provided, and the controller is configured to program the memory cells to respective threshold voltages in a programming operation. The controller is configured to, in the programming operation, apply a first voltage to a control gate of a selected word line of the plurality of word lines. The controller is also configured to continuously ramp a voltage applied to the control gate of the selected word line from the first voltage to a programming voltage over a first duration. The controller is further configured to hold the voltage applied to the control gate of the selected word line at the programming voltage over a second duration that is less than the first duration.

Programming techniques to reduce programming stress in a memory device

In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.

Non-volatile memory with tuning of erase process

A memory apparatus and method of operation are provided. The apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of memory cells and configured to retain a transistor threshold voltage. The memory holes are arranged in rows comprising strings. A control means is configured to program drain-side select gate transistors of the memory holes to an initial transistor threshold voltage using pulses increasing in magnitude by a first transistor step amount during each of a plurality of foggy loops of a foggy program operation. The control means is also configured to program the drain-side select gate transistors of the memory holes to a target transistor threshold voltage using pulses increasing in magnitude by a second transistor step amount during each of a plurality of fine loops of a fine program operation. The first transistor step amount is greater than the second transistor step amount.

Foggy-fine drain-side select gate re-program for on-pitch semi-circle drain side select gates

A method of operating a non-volatile semiconductor memory device is disclosed. The method comprises: during a first pre-read cycle of a read operation, ramping up a control signal on a wordline selected for the read operation to a first target pre-read voltage and ramping up a control signal on a drain-side select (SGD) transistor of an unselected string of the plurality of strings to a second target pre-read voltage. The method further comprises during a second pre-read cycle of the read operation, ramping down the control signal on the wordline to a target read voltage and ramping down the control signal on the SGD transistor of the unselected string to a third target pre-read voltage after a delay period after the triggering edge of the second pre-read cycle.

Pre-read cycle timing shrink by SGD bias control and page and wordline control

An apparatus includes a control circuit configured to connect to NAND strings that are connected to bit lines, where each bit line is connected to a plurality of NAND strings in a corresponding plurality of regions of a block. The control circuit is configured to apply a read voltage in read operations directed to NAND strings of the plurality of regions of the block and subsequently adjust the read voltage by a first predetermined amount for read operations directed to NAND strings of a first region of the block. The control circuit is further configured to adjust the read voltage by a second predetermined amount for read operations directed to NAND strings of a second region of the block. The first and second predetermined amounts are based on respective locations of the first and second regions in the block.

NAND string read voltage adjustment

In order to decrease the width of threshold voltage distributions of programmed memory cells without unreasonably increasing the time needed to complete programming, a non-volatile memory uses a zone based program speed adjustment. The non-volatile memory starts programming a first set of the non-volatile memory cells until a minimum number of memory cells of the first set of non-volatile memory cells reach a first threshold voltage. In response to the minimum number of memory cells reaching the first threshold voltage, the first set of non-volatile memory cells are categorized into zones/groups based on threshold voltage. The speed of programming is then adjusted differently for each zone/group and programming is completed for the first set of non-volatile memory cells.

Non-volatile memory with zone based program speed adjustment

A memory system having a dynamic supply voltage to sense amplifiers. The supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.

Dynamic sense amplifier supply voltage for power and die size reduction

In a non-volatile memory, to achieve a shallow and tight erased threshold voltage distribution, a process is performed that includes erasing a group of non-volatile memory cells, identifying a first set of the bit lines that are connected to non-volatile memory cells of the group that are erased past a lower limit for erased non-volatile memory cells and identifying a second set of the bit lines that are connected to non-volatile memory cells of the group that are not erased past the lower limit for erased non-volatile memory cells, and applying programming to non-volatile memory cells connected to the first set of bit lines while inhibiting programming for non-volatile memory cells connected to the second set of bit lines.

Non-volatile memory with narrow and shallow erase

A memory apparatus and method of operation is provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings coupled to one of a plurality of bit lines and are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to read each of the memory cells in a read operation. For each one of the memory cells, the control means is also configured to offset at least one of a bit line settling time and a kick voltage during the read operation based on a probability of at least one neighboring one of the plurality of bit lines being coupled to the memory cells retaining the threshold voltage corresponding to a different one of the plurality of data states than the one of the memory cells.

Utilizing data pattern effect to control read clock timing and bit line kick for read time reduction

A memory apparatus and method of operation are provided. The apparatus includes a page of memory cells connected to a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and strings and identifies the memory cells having the threshold voltage less than a primary demarcation threshold voltage of a series for demarcating between memory states in a page read. The control circuit also identifies the memory cells having the threshold voltage less than a secondary demarcation threshold voltage of the series. The control circuit supplies a near zero voltage to the strings of the memory cells identified as having the threshold voltages less than at least one of the primary and secondary demarcation threshold voltages to inhibit conduction currents while identifying the memory cells having the threshold voltage less than a tertiary demarcation threshold voltage.

Power saving and fast read sequence for non-volatile memory

An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a predicted parasitic capacitance associated with the programming state of the control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.

Peak current and program time optimization through loop dependent voltage ramp target and timing control

The non-volatile memory includes a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells of the plurality of word lines to a plurality of data states in a multi-pass programming operation. A later programming pass of the multi-pass programming operation includes a plurality of programming loops with incrementally increasing programming pulses. For at least one data state, the later programming pass includes maintaining a count of the programming loops of the later programming pass. The later programming pass also includes inhibiting or slowing programming of the memory cells being programmed to one of the data states during a predetermined program count verify (PCV) programming loop and a PCV&#x2212;1 programming loop and skipping a verify operation for all programming loops prior to a PCV+1 programming loop.

Memory programming with selectively skipped verify pulses for performance improvement

A processing chamber for processing a substrate is disclosed herein. In one embodiment, the processing chamber includes a liner assembly disposed within an interior volume of the processing chamber, and a C-channel disposed in an interior volume of the chamber, circumscribing the liner assembly. In another embodiment, a process kit disposed in the interior volume of the processing chamber is disclosed herein. The process kit includes a liner assembly, a C-channel, and an isolator disposed in the interior volume. The C-channel and the isolator circumscribe the liner assembly. A method for depositing a silicon based material on a substrate by flowing a precursor gas into a processing chamber is also described herein.

Growing community of inventors

Santa Clara, CA, United States of America

Yanjie Wang