Baltimore, MD, United States of America

Virantha N Ekanayake

This inventor holds 21 USPTO granted patents and 1 published patent application and 1 EPO patent, primarily in Asynchronous Circuits. Top assignee: Achronix Semiconductor Corporation. Active years: 2011-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Virantha N Ekanayake. Retrieved from https://idiyas.com/inventor/virantha-n-ekanayake

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 21 

% Patents Active = 100.0

 

Average Co-Inventor Count = 4.1

ph-index = 5

Forward Citations = 69(Granted Patents)


Location History:

  • San Jose, CA (US) (2011 - 2016)
  • Baltimore, MD (US) (2023 - 2024)

Company Filing History:


Years Active: 2011-2026

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Areas of Expertise:
FPGA Memory
Synchronous Reset
Adder Circuit
Pipelined Interconnect
Asynchronous Logic
Reset Mechanism
Programmable Structures
Token Enhanced Conversion
Multi-Clock Circuits
Circuit Representation
One Phase Logic
Asynchronous Conversion
21 patents (USPTO):Explore Patents

Title: **Innovations and Contributions of Virantha N Ekanayake**

Introduction

Virantha N Ekanayake is a prominent inventor based in Baltimore, MD, known for his significant contributions to the field of semiconductor technology. With a remarkable portfolio of 20 patents, he has made substantial advancements in circuit design and signal processing, particularly in the context of system-on-chip (SoC) architectures.

Latest Patents

Among his latest innovations are two notable patents: the **Synchronous Reset Deassertion Circuit** and the **Adder Circuit Using Lookup Tables**. The Synchronous Reset Deassertion Circuit addresses the challenge of distributing reset signals across SoCs by generating a synchronous reset signal that maintains a fixed timing relationship with the clock signal. This design ensures that the reset signal reaches all intellectual property (IP) blocks within a single clock cycle, improving the overall operating frequency of the device.

The Adder Circuit Using Lookup Tables showcases an innovative modification of a four-input lookup table (LUT4) that can function as both an ordinary LUT4 and as a 1-bit adder. Additionally, a six-input lookup table (LUT6) is adapted to serve as a 2-bit adder under specific conditions, allowing for efficient use of logic blocks in circuit designs.

Career Highlights

Virantha N Ekanayake has made significant strides in his career while working at **Achronix Semiconductor Corporation**. His expertise in semiconductor design and innovation has established him as a key figure within the company, contributing to advancements that enhance the performance and efficiency of semiconductor products.

Collaborations

Throughout his career, Virantha has collaborated with esteemed colleagues such as Rajit Manohar and Clinton W Kelly. These collaborations have fostered an environment of innovation and have propelled the development of groundbreaking technologies in the semiconductor industry.

Conclusion

In summary, Virantha N Ekanayake’s contributions to the field of circuit design and semiconductor technology are significant. With a strong portfolio of patents and a collaborative spirit, he continues to influence the landscape of innovation at Achronix Semiconductor Corporation, paving the way for future advancements in technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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