The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 16, 2024

Filed:

May. 08, 2023
Applicant:

Achronix Semiconductor Corporation, Santa Clara, CA (US);

Inventors:

Christopher C. LaFrieda, Ridgefield, NJ (US);

Virantha N. Ekanayake, Baltimore, MD (US);

Assignee:

Achronix Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/575 (2006.01); G06F 1/03 (2006.01); G06F 7/504 (2006.01); H03K 19/20 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
G06F 7/575 (2013.01); G06F 1/03 (2013.01); G06F 7/5045 (2013.01); H03K 19/20 (2013.01); H03K 19/21 (2013.01);
Abstract

A four-input lookup table ('LUT4') is modified to operate in a first mode as an ordinary LUT4 and in a second mode as a 1-bit adder providing a sum output and a carry output. A six-input lookup table (“LUT6”) is modified to operate in a first mode as an ordinary LUT6 with a single output and in a second mode as a 2-bit adder providing a sum output and a carry output. Both possible results for the two different possible carry inputs can be determined and selected between when the carry input is available, implementing a 2-bit carry-select adder when in the second mode and retaining the ability to operate as an ordinary LUT6 in the first mode. Using the novel LUT6 design in a circuit chip fabric allows a 2-bit adder slice to be built that efficiently makes use of the LUT6 without requiring additional logic blocks.


Find Patent Forward Citations

Loading…