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For the Inventor, By the Inventor

Santa Clara, CA, United States of America

Achronix Semiconductor Corporation


USPTO Granted Patents = 73


Trademarks = 3

Forward Citations = 336

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43 inventors (with patents filed for the assignee):

goldMedal Rajit Manohar (31 out of 53 patents)

silverMedal Raymond Nijssen (24 out of 25 patents)

bronzeMedal Clinton W Kelly (24 out of 24 patents)

4.  Virantha N Ekanayake (21 out of 21 patents)

5.  Marcel Van Der Goot (15 out of 15 patents)

6.  Christopher C LaFrieda (15 out of 15 patents)

7.  Daniel J Pugh (13 out of 26 patents)

8.  Kent Orthner (11 out of 27 patents)

9.  Sarma Jonnavithula (10 out of 10 patents)

10.  Michael Philip Fitton (10 out of 14 patents)

11.  Travis Johnson (8 out of 10 patents)

12.  Gael Paul (7 out of 12 patents)

13.  Quinn Jacobson (6 out of 6 patents)

14.  Rahul Nimaiyar (5 out of 5 patents)

15.  Mohan Krishna Vedam (5 out of 5 patents)


Core Competencies:
Asynchronous Logic
FPGA Architecture
Programmable Integrated Circuit
Reconfigurable Logic Fabrics
Network on a Chip
Fused Memory
Arithmetic Circuit
Parallel Sorting
Multi-Clock Logic
Synchronous Reset
Flexible Routing
Clock Tree

73 patents:

1. 12681893 - Processing of ethernet packets at a programmable integrated circuit (2026-07-14),
2. 12639007 - FPGA memory with auto address mode (2026-05-26),
3. 12632183 - Conflict-free parallel radix sorting device, system and method (2026-05-19),
4. 12567863 - Fused memory and arithmetic circuit (2026-03-03),
5. 12506696 - Sliced router for network on a chip (2025-12-23),
6. 12468506 - Multiple mode arithmetic circuit (2025-11-11),
7. 12332683 - Synchronous reset deassertion circuit (2025-06-17),
8. 12248764 - Adder circuit using lookup tables (2025-03-11),
9. 12224953 - Wide elastic buffer (2025-02-11),
10. 12197734 - Conflict-free parallel radix sorting device, system and method (2025-01-14),
11. 12185462 - Capacitive compensation for vertical interconnect accesses (2024-12-31),
12. 12174782 - Processing of ethernet packets at a programmable integrated circuit (2024-12-24),
13. 12141088 - Cascade communications between FPGA tiles (2024-11-12),
14. 12093623 - Relocatable FPGA modules (2024-09-17),
15. 12034446 - Fused memory and arithmetic circuit (2024-07-09),
Company Overview
Achronix Semiconductor Corporation, based in Santa Clara, California, specializes in advanced asynchronous circuit design and programmable integrated circuits. The company focuses on developing high-performance FPGA architectures and reconfigurable logic fabrics, which enable efficient processing for a variety of applications. Achronix's innovative technologies also encompass asynchronous logic, network on a chip solutions, and fused memory, catering to the growing demands of data-intensive environments and complex computational tasks.
Profile summary synthesized from public USPTO records and patent filings.

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USPTO Data Jan 1 1976 - Oct 13 2026

Achronix Semiconductor Corporation USPTO Patent Assignee Logo
73 Patents

#54 in Santa Clara, CA

#1,185 in California

#5,039 in US

#10,263 in the World

Santa Clara, CA (US)
Santa Clara, CA, United States of America

Achronix Semiconductor Corporation

Forward Citations = 336

43 inventors:

goldMedal Rajit Manohar (31 out of 53 patents)

silverMedal Raymond Nijssen (24 out of 25 patents)

bronzeMedal Clinton W Kelly (24 out of 24 patents)

4.  Virantha N Ekanayake (21 out of 21 patents)

5.  Marcel Van Der Goot (15 out of 15 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Achronix Semiconductor Corporation. Retrieved from https://idiyas.com/company/achronix-semiconductor

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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