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Berkeley, CA, United States of America

Viktor Salitrennik

USPTO Granted Patents = 8

Average Co-Inventor Count = 2.8

ph-index = 4

Forward Citations = 48(Granted Patents)

Location History:

Berkeley, CA (US) (2015 - 2017)
San Jose, CA (US) (2008 - 2019)

Company Filing History:

Cadence Design Systems, Inc.

Quickturn Design Systems, Inc.

Years Active: 2008-2019

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8 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10509877 - Systems and methods for reducing latency when transferring I/O between an emulator and target device (2019-12-17),

2. 9646120 - Method and system for trace compaction during emulation of a circuit design (2017-05-09),

3. 9372947 - Compacting trace data generated by emulation processors during emulation of a circuit design (2016-06-21),

4. 9298866 - Method and system for modeling a flip-flop of a user design (2016-03-29),

5. 9292639 - Method and system for providing additional look-up tables (2016-03-22),

6. 9171111 - Hardware emulation method and system using a port time shift register (2015-10-27),

7. 8959010 - Emulation system with improved reliability of interconnect and a method for programming such interconnect (2015-02-17),

8. 7379861 - Dynamic programming of trigger conditions in hardware emulation systems (2008-05-27),

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