Modeling of four-state-aware content-addressable memories in an emulation system

Abstract

The systems and methods described herein include an emulation system for modeling user integrated circuit (IC) designs having content-addressable memory (CAM) or ternary content-addressable memory (TCAM) design elements. The emulator includes compiling software performing synthesis and compiling operations that compile netlist logic for IC designs, including virtual instrumentation logic for handling administrative overhead functions. For a CAM/TCAM instance of the IC design, the emulator instantiates a wrapper comprising instrumentation logic that performs translation or transformation functions on inputs into the CAM/TCAM and on outputs produced from the CAM/TCAM, facilitating compatibility. The wrapper logic includes logic for modeling a CAM/TCAM search of the memory locations, including table-matching logic for comparing search query bits against the memory locations. The wrapper may further include error-handling logic for generating error messages in circumstances when the emulator or the IC design cannot handle the output of the CAM/TCAM.