Cadence Design Systems, Inc.

Quickturn Design Systems, Inc.

Viktor Salitrennik

Mitchell Grant Poplack

Beshara G Elmufdi

Alon Kfir

Mikhail Bershteyn

Gavin Zawalski

Systems, methods, and products having pipelined inputs to and outputs from an emulator are disclosed. Using a pipeline may allow the round trip cable delay (RTCD) to be spread across two or more clock cycles. In an embodiment, an emulation system may store input data received from a target device during a first clock cycle at a target timing domain interfacing component (TTD), and transmit the stored input data during a second clock cycle after the first clock cycle. In another embodiment, the emulation system may delay transmitting the input data received at the TTD during the first clock cycle such that that the input data reaches the emulator at a predetermined time during the second clock cycle. As the RTCD is spread across multiple clock cycles, the emulation system may implement faster clocks.

Systems and methods for reducing latency when transferring I/O between an emulator and target device

The present patent document relates to a method to compact trace data generated by emulation processors during emulation of a circuit design, and a hardware functional verification system that compacts trace data. Compaction logic within emulation processor clusters accumulated data bits output from the emulation processors and compacts them into trace data bytes in registers based on enable bits identifying valid trace data according to a compaction scheme. Trace data bytes are further accumulated and compacted into larger trace data bytes in higher level processor clusters of the emulation chip according to a compaction hierarchy, with the compacted trace data bytes stored into a trace array of the emulation chip.

Method and system for trace compaction during emulation of a circuit design

Compacting trace data generated by emulation processors during emulation of a circuit design

The present patent document relates to a method and apparatus for modeling a flip-flop of a user's circuit design when that circuit design is mapped in a hardware functional verification system including a plurality of interconnected emulation chips, or in a single emulation chip. The flip flop can be modeled in the emulation chip as two stages using only a single instruction, and may be configured by programming a register set. A data block, enable block, and LUT block are provided to model the flip flop, and may operate in one of several modes, including combined and uncombined modes. The data block includes a data array to store and provide previous data inputs and previous states of the modeled flip flop. The disclosed embodiments allow a more efficient use of LUTs for modeling flip flops, including options for resets and global enables, operating in several modes.

Method and system for modeling a flip-flop of a user design

A method and system of providing additional lookup tables in an emulation processor cluster of an emulation chip of a hardware functional verification system is provided. An indirection table may be used within the processor cluster to provide the commonly-used function tables for the lookup tables (LUTs). The indirection table may be indexed according to a smaller portion of the standard LUT function table provided by an instruction than otherwise needed. The unused function table bits in the instruction may then be used for other purposes, including providing functionality to one or more extra LUTs of the processor cluster, whose function tables may be provided from another indirection table provided for that purpose. Additional processing capacity may thereby be provided for the cluster with a small amount of additional overhead within the emulation chip, while still providing the full range of function tables of the LUTs.

Method and system for providing additional look-up tables

A processor-based hardware functional verification system with time shift registers is described. The system includes a processor cluster with a plurality of processors that each have a data inputs and select inputs. Furthermore, a plurality of electronic memories each having a plurality of read ports is associated with the processors, respectively. The time shift registers each have an input in communication with the read ports of the electronic memories and an output in communication with the select inputs of the processors. The system further includes an instruction memory that provides a control signal to each of the time shift registers to store data output from read ports of the electronic memories that can be provided to the processor for evaluation during a subsequent emulation step.

Hardware emulation method and system using a port time shift register

A method and apparatus for redundant communication channels in an emulation system is disclosed. A processor-based emulation system has a plurality of emulation chips on an emulation board. The emulation chips have a plurality of processor clusters. Signals are sent over one or more communication channels between processor clusters, including from a processor cluster on one emulation chip to a processor cluster on another emulation chip. Copies of the same signal may be sent in duplicate over separate communication channels. If a communication channel failure is detected, instruction memory is modified so that a processor cluster's instructions no longer address a first cluster memory location, but instead address a second cluster memory location of a non-failed communication channel. By using redundant communication channels, emulation system interconnect reliability is increased and recompilation of the design under verification may be avoided.

Emulation system with improved reliability of interconnect and a method for programming such interconnect

An improved emulation system having an improved trigger mechanism is disclosed. During the compilation of the circuit design, a portion of the emulation resources are reserved for dynamic netlists. The dynamic netlists allows a user to create arbitrary trigger circuits that can be based on any signal generated by the device under test during run time, including signals that were optimized out of the design during the compilation process. The dynamic netlists can be loaded and used in the emulator without having to recompile the entire design, which could take many hours. This enables a user to quickly and efficiently debug circuit designs.

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Berkeley, CA, United States of America

Viktor Salitrennik