The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2016
Filed:
Sep. 30, 2014
Cadence Design Systems, Inc., San Jose, CA (US);
Beshara Elmufdi, San Jose, CA (US);
Mitchell G. Poplack, San Jose, CA (US);
Viktor Salitrennik, Berkeley, CA (US);
CADENCE DESIGN SYSTEMS INC., San Jose, CA (US);
Abstract
The present patent document relates to a method and apparatus for modeling a flip-flop of a user's circuit design when that circuit design is mapped in a hardware functional verification system including a plurality of interconnected emulation chips, or in a single emulation chip. The flip flop can be modeled in the emulation chip as two stages using only a single instruction, and may be configured by programming a register set. A data block, enable block, and LUT block are provided to model the flip flop, and may operate in one of several modes, including combined and uncombined modes. The data block includes a data array to store and provide previous data inputs and previous states of the modeled flip flop. The disclosed embodiments allow a more efficient use of LUTs for modeling flip flops, including options for resets and global enables, operating in several modes.