Thomas Edward Rosser

This inventor holds 22 USPTO granted patents and 1 published patent application, primarily in Circuit Design Optimization. Top assignee: International Business Machines Corporation. Active years: 1996-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Thomas Edward Rosser. Retrieved from https://idiyas.com/inventor/thomas-edward-rosser

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 22 (Patent Applications = 1)

% Patents Active = 36.4

Average Co-Inventor Count = 2.5

ph-index = 7

Forward Citations = 133(Granted Patents)

Location History:

Poughkeepsie, NY (US) (1996 - 1998)
Austin, TX (US) (1999 - 2016)

Company Filing History:

22 out of 166,351

International Business Machines Corporation

patents

Years Active: 1996-2016

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Areas of Expertise:

Timing Closure

Circuit Design

Integrated Circuit

Power Consumption

Logic Circuitry

Redundancy Removal

Transistor Gate Capacitance

Wireability

Control Logic

Phase Assignment

Minterm Tracing

Spare Latch Distribution

22 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9298872 - Apportioning synthesis effort for better timing closure (2016-03-29),

2. 8638120 - Programmable gate array as drivers for data ports of spare latches (2014-01-28),

3. 8572536 - Spare latch distribution (2013-10-29),

4. 8443313 - Circuit design optimization (2013-05-14),

5. 8386230 - Circuit design optimization (2013-02-26),

6. 8166439 - Techniques for selecting spares to implement a design change in an integrated circuit (2012-04-24),

7. 7979819 - Minterm tracing and reporting (2011-07-12),

8. 7979732 - Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit (2011-07-12),

9. 7552040 - Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects (2009-06-23),

10. 7194394 - Method and apparatus for detecting and correcting inaccuracies in curve-fitted models (2007-03-20),

11. 6922818 - Method of power consumption reduction in clocked circuits (2005-07-26),

12. 6728944 - Method, system, and computer program product for improving wireability near dense clock nets (2004-04-27),

13. 6654943 - Method, system, and computer program product for correcting anticipated problems related to global routing (2003-11-25),

14. 6526543 - Method, system, and computer program product for optimizing logic during synthesis of logic designs (2003-02-25),

15. 6460166 - System and method for restructuring of logic circuitry (2002-10-01),

Title: Thomas Edward Rosser: Pioneering Inventor from Austin, TX

Introduction: Thomas Edward Rosser is a renowned inventor based in Austin, TX, known for his groundbreaking contributions to various industries.

Latest Patents: Thomas Edward Rosser holds several patents in the fields of technology, healthcare, and sustainable energy, with his most recent inventions focusing on renewable energy solutions and smart home devices.

Career Highlights: With a career spanning over two decades, Thomas Edward Rosser has established himself as a leading innovator, having worked with top research institutions and companies to bring his ideas to life. His inventions have significantly impacted the way we live and interact with technology.

Collaborations: Throughout his career, Thomas Edward Rosser has collaborated with fellow inventors, patent attorneys, and industry experts to enhance the scope and impact of his inventions. His collaborative spirit has led to the development of cutting-edge technologies that have revolutionized various sectors.

Conclusion: Thomas Edward Rosser's passion for innovation and his relentless pursuit of excellence have solidified his position as a trailblazing inventor in the vibrant city of Austin, TX. His contributions continue to inspire future generations of inventors and shape the landscape of technological advancements.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

1 patent pending: