International Business Machines Corporation

Thomas Edward Rosser

Ruchir Puri

Lakshmi Narasimha Reddy

Joachim Gerhard Clabes

Andrew Augustus Bjorksten

Kevin Franklin Reick

Samuel I Ward

Sridhar H Rangarajan

Bryan J Robbins

Robert J Shadowen

Barry Lee Dorfman

Jeremy T Hopkins

Prashant Srinivasrao Sawkar

Paul William Horstmann

Gi-Joon Nam

James Douglas Warnock

Sam Gat-Shang Chu

Jeffrey Paul Soreff

Lawrence D Curley

Arjen Alexander Mets

George Antony

Manikandan Viswanath

Travis Wellington Pouarz

John Mack Isakson

Michael Normand Goulet

Ashish Jaitly

Kristen M Tucker

Timing for a critical path of a circuit design is optimized by splitting up the path so the synthesis effort to solve the path is appropriately apportioned. Selected nodes of the path are made visible, and internal timing constraints are applied to gates at the visible nodes. The internal timing constraints are translated into physical locations, and placement constraints are applied to the gates based on the physical locations, followed by timing-driven placement. The internal timing constraints can be required arrival times computed using a linear delay model. The placement constraints can include an attractive force between a given one of the selected gates and a corresponding one of the physical locations. The results are better stability control from run to run, and significant savings in power consumption due to less buffering and better gate sizing, with an optimum partition of the path for better routing.

Apportioning synthesis effort for better timing closure

Aspects of the invention provide for improving a success rate of an engineering design change (ECO) for an integrated circuit. In one embodiment, aspects of the invention include a method for improving a success rate of an engineering design change (ECO) for an integrated circuit, including: identifying a plurality of spare latches within the integrated circuit; determining an input driver for each of the spare latches; and replacing each input driver with a programmable gate array, such that the programmable gate array is programmed to a functionality of the input driver.

Programmable gate array as drivers for data ports of spare latches

Aspects of the invention provide for spare latch distribution for an integrated circuit design. In one embodiment, aspects of the invention include a method of generating a computer system for spare latch distribution in an integration circuit design, the method including: providing a computer system operable to: receive design data for the integrated circuit design, the design data including a plurality of latches; segment the integrated circuit design into a plurality of equal sections; determine a latch density within each of the equal sections; and determine a number of spare latches, based on the latch density, for each of the equal sections. Further, it is understood that the above are performed for each clock domain within the integrated circuit design.

Spare latch distribution

A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout path, and a logic cone. The first master latch couples to the first fanout path and is configured to receive a first data input signal. The first fanout path comprises a plurality of output sinks, each coupled to the logic cone. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit and an abstract latch clone based on the first master latch. A configuration file is generated based on the second behavioral model. The configuration file comprises information representing a plurality of instantiated latch clones based on the abstract latch clone, each configured to couple to the first data input signal and to one or more output sinks of the plurality of output sinks. The second behavioral model and the configuration file are together configured for input to a synthesis tool.

Circuit design optimization

A method includes generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration. The first configuration comprises a first logic structure configured to generate a first intermediate signal based on a received first plurality of inputs. The first configuration further comprises a logic cone configured to generate a scan output based on the first intermediate signal and a plurality of scan inputs. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit configured to receive the scan output and the first intermediate signal. A testability model is generated based on the second behavioral model, the testability model comprising a first structural representation of the first logic structure. In the event the first logic structure causes a coverage problem, the testability model is modified to include an inversion structure. The inversion structure is configured based on the first logic structure. The inversion structure is configured to generate an inversion structure output. The testability model is modified to couple the inversion structure output as an input to the error circuit.

A technique for implementing an engineering change order includes determining spares that are available to implement a modification to a circuit design. One of the available spares is then selected to implement the modification to the circuit design based on performance criteria associated with each of the available spares.

Techniques for selecting spares to implement a design change in an integrated circuit

A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.

Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit

Disclosed are a method, a system and a computer program product for determining and reporting minterms to aid in implementing an engineering change order (ECO). A Minterm Tracing and Reporting (MTR) utility, which executes on a computer system, receives two or more timing points of an optimized netlist, where one or more of the two or more timing points are received from one or more of a user, a memory medium, and/or a network. For example, a timing point is a primary input, a primary output, or a latch point. After receiving the two or more timing points of the optimized netlist, the MTR utility determines two or more minterms of the optimized netlist. In determining the minterms, from one timing point to a next timing point: a polarity at the timing point may be determined, and a forward trace from the timing point to the next timing point is performed to determine the two or more minterms of the optimized netlist. In the forward trace from the timing point to the next timing point, the MTR utility determines two or more logical cones and one or more intersections of the logical cones. The MTR utility reports (e.g., communicates) each of the determined minterms, the determined polarities, and the one or more intersections of logical cones to one or more of a computer-executable application, a network, a memory medium, and/or a display.

Minterm tracing and reporting

A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.

Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects

A technique for detecting and correcting inaccuracies in curve-fitted models. Humps and dips in a curve-fitted model are identified. An analysis is performed on the humps and dips to determine if they are large enough to warrant correction. If so, then the source of the simulation and/or empirical data is modified to taking corrective action to improve the curve fit between the edge point and the next actual simulation and/or empirical data point.

Method and apparatus for detecting and correcting inaccuracies in curve-fitted models

A method and apparatus for reducing power consumption of a clocked circuit containing a plurality of latches is provided. A first latch, within the plurality of latches, is located which has more than a predetermined slack. The possibility of substituting an available second latch, that requires less power to operate, is then determined, subject to the constraint that the slack after substitution should still be positive, although it may be less than the predetermined number mentioned above. Where such a possibility is determined to exist, the first latch is then replaced with the available second latch.

Method of power consumption reduction in clocked circuits

A method, system, and computer product are disclosed for improving wireability near clock nets in a logic design that includes multiple logic blocks. Each of the logic blocks has an actual physical size. Logic blocks that are a particular type are identified. During placement of the logic blocks, an apparent physical size of each of the identified logic blocks is utilized as a physical size for the identified logic block. The apparent physical size is larger than the actual physical size. During routing, the actual physical size of each of the identified logic blocks is utilized.

Method, system, and computer program product for improving wireability near dense clock nets

A method, system, and computer product are disclosed for correcting anticipated problems related to global routing during logic synthesis. Synthesis is begun of a circuit design that includes multiple logic functions. During the synthesis, multiple logic books are selected to use to implement the logic function. Also during synthesis, at least one of the logic books is identified that is sensitive to a change in output wire capacitance of the identified logic book, where a value of the output wire capacitance is related to a routing of the wire. A strength of each identified logic book is then increased.

Method, system, and computer program product for correcting anticipated problems related to global routing

A method, system, and computer program product are disclosed for optimizing logic during synthesis of a logic design. A first timing path within the logic design is identified. The first timing path has first logic to be optimized in order to improve timing in the first timing path. A determination is then made regarding whether an input node to the first timing path is a particular device. In response to the input node being the particular device, a determination is made regarding whether optimizing second logic included in a second timing path having the particular device as its output node will improve timing in the first timing path. In response to a determination that optimizing the second logic will improve timing in the first timing path, both the second logic and the first logic are selected to be optimized.

Method, system, and computer program product for optimizing logic during synthesis of logic designs

An algorithm for efficient restructuring of logic circuitry to improve selected characteristics (delay and/or area). Along a path through the logic circuitry, the logic is converted to equivalent implementations with the same Boolean function using specific choices from the library of available cells, such that these conversions provide an improvement in the cost/benefit for the selected characteristics.

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Austin, TX, United States of America

Thomas Edward Rosser