The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6526543 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 25, 2003

Filed:

Nov. 29, 2001
Applicant:
Inventor:

Thomas Edward Rosser, Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ; G06F 9/45 ;
U.S. Cl.
CPC ...
G06F 1/750 ; G06F 9/45 ;
Abstract

A method, system, and computer program product are disclosed for optimizing logic during synthesis of a logic design. A first timing path within the logic design is identified. The first timing path has first logic to be optimized in order to improve timing in the first timing path. A determination is then made regarding whether an input node to the first timing path is a particular device. In response to the input node being the particular device, a determination is made regarding whether optimizing second logic included in a second timing path having the particular device as its output node will improve timing in the first timing path. In response to a determination that optimizing the second logic will improve timing in the first timing path, both the second logic and the first logic are selected to be optimized.


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