The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 26, 2013
Filed:
Aug. 18, 2010
Samuel I. Ward, Austin, TX (US);
Kevin F. Reick, Round Rock, TX (US);
Bryan J. Robbins, Poughkeepsie, NY (US);
Thomas E. Rosser, Austin, TX (US);
Robert J. Shadowen, Austin, TX (US);
Samuel I. Ward, Austin, TX (US);
Kevin F. Reick, Round Rock, TX (US);
Bryan J. Robbins, Poughkeepsie, NY (US);
Thomas E. Rosser, Austin, TX (US);
Robert J. Shadowen, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method includes generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration. The first configuration comprises a first logic structure configured to generate a first intermediate signal based on a received first plurality of inputs. The first configuration further comprises a logic cone configured to generate a scan output based on the first intermediate signal and a plurality of scan inputs. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit configured to receive the scan output and the first intermediate signal. A testability model is generated based on the second behavioral model, the testability model comprising a first structural representation of the first logic structure. In the event the first logic structure causes a coverage problem, the testability model is modified to include an inversion structure. The inversion structure is configured based on the first logic structure. The inversion structure is configured to generate an inversion structure output. The testability model is modified to couple the inversion structure output as an input to the error circuit.