Apportioning synthesis effort for better timing closure

Abstract

Timing for a critical path of a circuit design is optimized by splitting up the path so the synthesis effort to solve the path is appropriately apportioned. Selected nodes of the path are made visible, and internal timing constraints are applied to gates at the visible nodes. The internal timing constraints are translated into physical locations, and placement constraints are applied to the gates based on the physical locations, followed by timing-driven placement. The internal timing constraints can be required arrival times computed using a linear delay model. The placement constraints can include an attractive force between a given one of the selected gates and a corresponding one of the physical locations. The results are better stability control from run to run, and significant savings in power consumption due to less buffering and better gate sizing, with an optimum partition of the path for better routing.