The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2011
Filed:
Jul. 03, 2007
Lawrence D. Curley, Round Rock, TX (US);
John M. Isakson, Austin, TX (US);
Arjen Mets, Sleepy Hollow, NY (US);
Travis W. Pouarz, Austin, TX (US);
Thomas E. Rosser, Austin, TX (US);
Kristen M. Tucker, Austin, TX (US);
Lawrence D. Curley, Round Rock, TX (US);
John M. Isakson, Austin, TX (US);
Arjen Mets, Sleepy Hollow, NY (US);
Travis W. Pouarz, Austin, TX (US);
Thomas E. Rosser, Austin, TX (US);
Kristen M. Tucker, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.