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For the Inventor, By the Inventor

Portland, OR, United States of America

Szuya S Liao

This inventor holds 51 USPTO granted patents and 16 published patent applications, primarily in Semiconductor Devices. Top assignees: Intel Corporation, Daedalus Prime LLC, Mediatek Corporation. Active years: 2017-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Szuya S Liao. Retrieved from https://idiyas.com/inventor/szuya-s-liao

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 51 

% Patents Active = 98.0

Average Co-Inventor Count = 4.3

ph-index = 4

Forward Citations = 90(Granted Patents)

Forward Citations (Not Self Cited) = 68(Dec 10, 2025)


Location History:

  • Hillsboro, OR (US) (2017 - 2023)
  • Portland, OR (US) (2019 - 2024)

Company Filing History:

goldMedal49 out of 56,290 
 
Intel Corporation
 patents
silverMedal1 out of 9 
 
Daedalus Prime LLC
 patents
bronzeMedal1 out of 5,091 
 
Mediatek Corporation
 patents

Years Active: 2017-2026

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Areas of Expertise:
SAGE Architectures
FinFETs
Contact Architectures
Epitaxial Regions
Semiconductor Devices
Transistor Structures
Capacitance Reduction
Doping Methods
Nanowire Devices
Hybrid Gate Spacers
Electrical Testing
Tensile Strain Techniques
51 patents (USPTO):Explore Patents
1. 12641840 - Self-aligned gate edge and local interconnect (2026-05-26),
2. 12426299 - Fin shaping and integrated circuit structures resulting therefrom (2025-09-23),
3. 12272688 - Selective growth self-aligned gate endcap (SAGE) architectures without fin end gap (2025-04-08),
4. 12266536 - Mid-processing removal of semiconductor fins during fabrication of integrated circuit structures (2025-04-01),
5. 12224326 - Contact architecture for capacitance reduction and satisfactory contact resistance (2025-02-11),
6. 12094955 - Confined epitaxial regions for semiconductor devices (2024-09-17),
7. 12027417 - Source or drain structures with high germanium concentration capping layer (2024-07-02),
8. 11984506 - Field effect transistor having a gate dielectric with a dipole layer and having a gate stressor layer (2024-05-14),
9. 11908940 - Field effect transistor with a hybrid gate spacer including a low-k dielectric material (2024-02-20),
10. 11901457 - Fin shaping and integrated circuit structures resulting therefrom (2024-02-13),
11. 11887860 - Mid-processing removal of semiconductor fins during fabrication of integrated circuit structures (2024-01-30),
12. 11869889 - Self-aligned gate endcap (SAGE) architectures without fin end gap (2024-01-09),
13. 11854894 - Integrated circuit device structures and double-sided electrical testing (2023-12-26),
14. 11824097 - Contact architecture for capacitance reduction and satisfactory contact resistance (2023-11-21),
15. 11688792 - Dual self-aligned gate endcap (SAGE) architectures (2023-06-27),

Title: Inventor Szuya S Liao - Pioneering Innovations in Portland

Introduction: Szuya S Liao is a distinguished inventor based in Portland, Oregon, known for his groundbreaking contributions to various fields of technology and science.

Latest Patents: Szuya S Liao holds several patents in the areas of renewable energy, sustainable materials, and advanced robotics, showcasing his commitment to creating a more sustainable future.

Career Highlights: With a career spanning over two decades, Szuya S Liao has worked with leading research institutions and universities to develop cutting-edge technologies that have revolutionized industries worldwide.

Collaborations: Throughout his career, Szuya S Liao has collaborated with top companies, innovative startups, and brilliant minds in the field, fostering a culture of creativity and innovation.

Conclusion: Szuya S Liao's passion for innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors and shape the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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