The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2024
Filed:
Sep. 23, 2019
Intel Corporation, Santa Clara, CA (US);
Szuya S. Liao, Portland, OR (US);
Scott B. Clendenning, Portland, OR (US);
Jessica Torres, Portland, OR (US);
Lukas Baumgartel, Portland, OR (US);
Kiran Chikkadi, Hillsboro, OR (US);
Diane Lancaster, Hillsboro, OR (US);
Matthew V. Metz, Portland, OR (US);
Florian Gstrein, Portland, OR (US);
Martin M. Mitan, Beaverton, OR (US);
Rami Hourani, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Self-aligned gate endcap (SAGE) architectures without fin end gaps, and methods of fabricating self-aligned gate endcap (SAGE) architectures without fin end gaps, are described. In an example, an integrated circuit structure includes a semiconductor fin having a cut along a length of the semiconductor fin. A gate endcap isolation structure has a first portion parallel with the length of the semiconductor fin and is spaced apart from the semiconductor fin. The gate endcap isolation structure also has a second portion in a location of the cut of the semiconductor fin and in contact with the semiconductor fin.