The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 11, 2025

Filed:

Oct. 10, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rishabh Mehandru, Portland, OR (US);

Pratik A. Patel, Portland, OR (US);

Ralph T. Troeger, Portland, OR (US);

Szuya S. Liao, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/321 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4175 (2013.01); H01L 21/02576 (2013.01); H01L 21/02579 (2013.01); H01L 21/0262 (2013.01); H01L 21/26513 (2013.01); H01L 21/30604 (2013.01); H01L 21/32115 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/45 (2013.01); H01L 29/4991 (2013.01); H01L 29/665 (2013.01); H01L 29/6656 (2013.01);
Abstract

Solid assemblies having a composite dielectric spacer and processes for fabricating the solid assemblies are provided. The composite dielectric spacer can include, in some embodiments, a first dielectric layer and a second dielectric layer having a mutual interface. The composite dielectric spacer can separate a contact member from a conductive interconnect member, thus reducing the capacitance between such members with respect to solid assemblies that include one of first dielectric layer or the second dielectric layer. The composite dielectric spacer can permit maintaining the real estate of an interface between the conductive interconnect and a trench contact member that has an interface with a carrier-doped epitaxial layer embodying or constituting a source contact region or a drain contact region of a field effect transistor. The trench contact member can form another interface with the conductive interconnect member, providing a satisfactory contact resistance therebetween.


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