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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11854894 B1

PDFFull Text
Date of Patent:
Dec. 26, 2023

Filed:

Dec. 04, 2020

Integrated circuit device structures and double-sided electrical testing

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Valluri R. Rao, Saratoga, CA (US);

Patrick Morrow, Portland, OR (US);

Rishabh Mehandru, Portland, OR (US);

Doug Ingerly, Portland, OR (US);

Kimin Jun, Portland, OR (US);

Kevin O'Brien, Portland, OR (US);

Paul Fischer, Portland, OR (US);

Szuya S. Liao, Portland, OR (US);

Bruce Block, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Essential Patents Group, LLP

Primary Examiner:

Jesse Y Miyoshi

Int. Cl.
CPC ...
H01L 21/822 (2006.01); H01L 21/306 (2006.01); H01L 21/683 (2006.01); H01L 21/8238 (2006.01); H01L 21/66 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); G01R 1/073 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 21/8221 (2013.01); H01L 21/30625 (2013.01); H01L 21/6835 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 22/14 (2013.01); H01L 23/528 (2013.01); H01L 23/53233 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 27/0924 (2013.01); H01L 27/1207 (2013.01); H01L 29/04 (2013.01); H01L 29/0696 (2013.01); H01L 29/0847 (2013.01); H01L 29/16 (2013.01); H01L 29/20 (2013.01); G01R 1/07307 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 27/1214 (2013.01); H01L 27/1222 (2013.01); H01L 29/66545 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68363 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/08147 (2013.01); H01L 2225/06565 (2013.01);
Abstract

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

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