Sung-Woo Han

This inventor holds 23 USPTO granted patents and 3 published patent applications, primarily in Semiconductor Technology. Top assignees: Hynix Semiconductor Inc., Skhynix Inc.. Active years: 2010-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sung-Woo Han. Retrieved from https://idiyas.com/inventor/sung-woo-han-bycefzpy

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 23 (Patent Applications = 3)

% Patents Active = 56.5

Average Co-Inventor Count = 9.7

ph-index = 5

Forward Citations = 65(Granted Patents)

Location History:

Ichon-shi, KR (2010)
Ichon, KR (2010 - 2012)
Gyeonggi-do, KR (2010 - 2016)

Company Filing History:

20 out of 6,228

Hynix Semiconductor Inc.

Years Active: 2010-2016

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Areas of Expertise:

Reservoir Capacitor

Input Buffer Circuit

Power-Sharing

Low Power Variable Delay

Voltage Regulator

Latency Control Circuit

Sampling Circuit

Duty Cycle Correction

Delay Locked Loop

Power Noise Detection

Semiconductor Memory Device

Integrated Circuit

23 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9276500 - Reservoir capacitor and semiconductor device including the same (2016-03-01),

2. 8461878 - Input buffer circuit of semiconductor apparatus (2013-06-11),

3. 8339159 - Input buffer circuit of semiconductor apparatus (2012-12-25),

4. 8283804 - Semiconductor IC device having power-sharing and method of power-sharing thereof (2012-10-09),

5. 8278981 - Low power variable delay circuit (2012-10-02),

6. 8144531 - Latency control circuit, semiconductor memory device including the same, and method for controlling latency (2012-03-27),

7. 8144530 - Semiconductor memory device and method for generating output enable signal (2012-03-27),

8. 8143940 - Internal supply voltage generating circuit and method for generating internal supply voltage (2012-03-27),

9. 8120416 - Semiconductor integrated circuit (2012-02-21),

10. 8076964 - Sampling circuit (2011-12-13),

11. 8035431 - Delay locked loop and delay locking method having burst tracking scheme (2011-10-11),

12. 8026701 - Voltage regulator for a synchronous clock system to reduce clock tree jitter (2011-09-27),

13. 8023356 - Voltage level comparison circuit of semiconductor memory apparatus, voltage adjustment circuit using voltage level comparison circuit, and semiconductor memory apparatus using the same (2011-09-20),

14. 7952364 - Power noise detecting device and power noise control device using the same (2011-05-31),

15. 7936620 - Receiver of semiconductor memory apparatus (2011-05-03),

Title: Sung-Woo Han: Pioneering Inventor from Gyeonggi-do, KR

Introduction: Sung-Woo Han is a distinguished inventor hailing from Gyeonggi-do, South Korea, known for his groundbreaking contributions to the field of technology and innovation.

Latest Patents: Sung-Woo Han holds several patents in the areas of electronics, telecommunications, and renewable energy, showcasing his versatility and ingenuity in creating cutting-edge solutions.

Career Highlights: With a career spanning over two decades, Sung-Woo Han has worked with leading tech companies, research institutions, and universities, where he has spearheaded numerous projects that have revolutionized the industry.

Collaborations: Sung-Woo Han has collaborated with top engineers, scientists, and designers from around the world, fostering a culture of innovation and excellence in all his endeavors. His collaborative spirit has led to the development of transformative technologies that have impacted society positively.

Conclusion: Sung-Woo Han's relentless passion for innovation, coupled with his exceptional technical skills, has solidified his position as a trailblazer in the world of inventions. His work continues to inspire future generations of inventors and researchers to push the boundaries of what is possible in the realm of technology.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

3 patents pending: