The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2011
Filed:
Jun. 12, 2009
Tae-jin Hwang, Gyeonggi-do, KR;
Yong-ju Kim, Gyenoggi-Do, KR;
Sung-woo Han, Gyeonggi-do, KR;
Hee-woong Song, Gyeonggi-do, KR;
Ic-su OH, Gyeonggi-do, KR;
Hyung-soo Kim, Gyeonggi-do, KR;
Hae-rang Choi, Gyeonggi-do, KR;
Ji-wang Lee, Gyeonggi-do, KR;
Jae-min Jang, Gyeonggi-do, KR;
Chang-kun Park, Gyeonggi-do, KR;
Tae-Jin Hwang, Gyeonggi-do, KR;
Yong-Ju Kim, Gyenoggi-Do, KR;
Sung-Woo Han, Gyeonggi-do, KR;
Hee-Woong Song, Gyeonggi-do, KR;
Ic-Su Oh, Gyeonggi-do, KR;
Hyung-Soo Kim, Gyeonggi-do, KR;
Hae-Rang Choi, Gyeonggi-do, KR;
Ji-Wang Lee, Gyeonggi-do, KR;
Jae-Min Jang, Gyeonggi-do, KR;
Chang-Kun Park, Gyeonggi-do, KR;
Hynix Semiconductor Inc., Gyeonggi-do, KR;
Abstract
A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level.