The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2011
Filed:
Nov. 06, 2008
Hyung-soo Kim, Gyeonggi-do, KR;
Yong-ju Kim, Gyeonggi-do, KR;
Sung-woo Han, Gyeonggi-do, KR;
Hee-woong Song, Gyeonggi-do, KR;
Ic-su OH, Gyeonggi-do, KR;
Tae-jin Hwang, Gyeonggi-do, KR;
Hae-rang Choi, Gyeonggi-do, KR;
Ji-wang Lee, Gyeonggi-do, KR;
Jae-min Jang, Gyeonggi-do, KR;
Chang-kun Park, Gyeonggi-do, KR;
Hyung-Soo Kim, Gyeonggi-do, KR;
Yong-Ju Kim, Gyeonggi-do, KR;
Sung-Woo Han, Gyeonggi-do, KR;
Hee-Woong Song, Gyeonggi-do, KR;
Ic-Su Oh, Gyeonggi-do, KR;
Tae-Jin Hwang, Gyeonggi-do, KR;
Hae-Rang Choi, Gyeonggi-do, KR;
Ji-Wang Lee, Gyeonggi-do, KR;
Jae-Min Jang, Gyeonggi-do, KR;
Chang-Kun Park, Gyeonggi-do, KR;
Hynix Semiconductor Inc., Gyeonggi-do, KR;
Abstract
A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains.