The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2012
Filed:
Dec. 08, 2009
Hae-rang Choi, Gyeonggi-do, KR;
Yong-ju Kim, Gyeonggi-do, KR;
Sung-woo Han, Gyeonggi-do, KR;
Hee-woong Song, Gyeonggi-do, KR;
Ic-su OH, Gyeonggi-do, KR;
Hyung-soo Kim, Gyeonggi-do, KR;
Tae-jin Hwang, Gyeonggi-do, KR;
Ji-wang Lee, Gyeonggi-do, KR;
Jae-min Jang, Gyeonggi-do, KR;
Chang-kun Park, Gyeonggi-do, KR;
Hae-Rang Choi, Gyeonggi-do, KR;
Yong-Ju Kim, Gyeonggi-do, KR;
Sung-Woo Han, Gyeonggi-do, KR;
Hee-Woong Song, Gyeonggi-do, KR;
Ic-Su Oh, Gyeonggi-do, KR;
Hyung-Soo Kim, Gyeonggi-do, KR;
Tae-Jin Hwang, Gyeonggi-do, KR;
Ji-Wang Lee, Gyeonggi-do, KR;
Jae-Min Jang, Gyeonggi-do, KR;
Chang-Kun Park, Gyeonggi-do, KR;
Hynix Semiconductor Inc., Gyeonggi-do, KR;
Abstract
A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information.