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For the Inventor, By the Inventor

Bangkok, Thailand

Suebphong Yenrudee

This inventor holds 16 USPTO granted patents. Top assignees: Utac Headquarters Pte. Ltd., Utac Thai Limited. Active years: 2015-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Suebphong Yenrudee. Retrieved from https://idiyas.com/inventor/suebphong-yenrudee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 16

% Patents Active = 100.0

Average Co-Inventor Count = 2.3

ph-index = 2

Forward Citations = 21(Granted Patents)


Company Filing History:

goldMedal14 out of 78 
 
Utac Headquarters Pte. Ltd.
 patents
silverMedal2 out of 50 
 
Utac Thai Limited
 patents

Years Active: 2015-2020

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16 patents (USPTO):Explore Patents
1. 10734247 - Semiconductor package with multiple molding routing layers and a method of manufacturing the same (2020-08-04),
2. 10600741 - Semiconductor package with plated metal shielding and a method thereof (2020-03-24),
3. 10361146 - Semiconductor package with multiple stacked leadframes and a method of manufacturing the same (2019-07-23),
4. 10325782 - Semiconductor package with multiple molding routing layers and a method of manufacturing the same (2019-06-18),
5. 10276477 - Semiconductor package with multiple stacked leadframes and a method of manufacturing the same (2019-04-30),
6. 10269686 - Method of improving adhesion between molding compounds and an apparatus thereof (2019-04-23),
7. 10242953 - Semiconductor package with plated metal shielding and a method thereof (2019-03-26),
8. 10163658 - Semiconductor package with multiple molding routing layers and a method of manufacturing the same (2018-12-25),
9. 10096490 - Semiconductor package with multiple molding routing layers and a method of manufacturing the same (2018-10-09),
10. 10032645 - Semiconductor package with multiple molding routing layers and a method of manufacturing the same (2018-07-24),
11. 9922843 - Semiconductor package with multiple molding routing layers and a method of manufacturing the same (2018-03-20),
12. 9917038 - Semiconductor package with multiple molding routing layers and a method of manufacturing the same (2018-03-13),
13. 9805955 - Semiconductor package with multiple molding routing layers and a method of manufacturing the same (2017-10-31),
14. 9449900 - Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow (2016-09-20),
15. 9029198 - Methods of manufacturing semiconductor devices including terminals with internal routing interconnections (2015-05-12),

Title: Suebphong Yenrudee: Innovator in Semiconductor Packaging

Introduction

Suebphong Yenrudee is a prominent inventor based in Bangkok, Thailand. He has made significant contributions to the field of semiconductor packaging, holding a total of 16 patents. His innovative approaches have advanced the technology used in semiconductor manufacturing.

Latest Patents

Yenrudee's latest patents include a semiconductor package with multiple molding routing layers and a method of manufacturing the same. This invention focuses on creating an internal routing circuit formed from multiple molding routing layers in a leadframe land grid array semiconductor package. The method utilizes a laser to remove undesired conductive areas, thereby establishing conductive paths on each molding compound layer. Another notable patent is for a semiconductor package with plated metal shielding and a method thereof. This method involves roughening the surfaces of a molding compound to enhance adhesion for metal plating, ensuring a more effective manufacturing process.

Career Highlights

Throughout his career, Suebphong Yenrudee has worked with notable companies such as Utac Headquarters Pte. Ltd. and Utac Thai Limited. His experience in these organizations has allowed him to refine his skills and contribute to groundbreaking advancements in semiconductor technology.

Collaborations

Yenrudee has collaborated with talented individuals in the industry, including Saravuth Sirinorakul and Chanapat Kongpoung. These partnerships have fostered a creative environment that

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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