The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2015
Filed:
Mar. 26, 2013
Applicant:
Utac Thai Limited, Bangkok, TH;
Inventors:
Saravuth Sirinorakul, Bangkok, TH;
Suebphong Yenrudee, Bangkok, TH;
Assignee:
UTAC Thai Limited, Bangna Bangkok, TH;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/498 (2006.01); H01L 23/48 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 23/481 (2013.01); H01L 21/78 (2013.01); H01L 24/97 (2013.01); H01L 2224/16 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/15311 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/45144 (2013.01); H01L 23/3128 (2013.01); H01L 2924/01047 (2013.01);
Abstract
A method of fabricating a semiconductor package includes forming a plurality of terminals on a sheet carrier, molding the sheet carrier with a first molding compound, creating electrical paths for a first routing layer, plating the first routing layer, placing dice on the first routing layer, encapsulating the dice with a second molding compound, removing at least a portion of the sheet carrier, and singulating the package from other packages.