Stefan Graef

This inventor holds 25 USPTO granted patents, primarily in Integrated Circuit Design. Top assignees: Lsi Logic Corporation, Formfactor, Inc.. Active years: 1998-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Stefan Graef. Retrieved from https://idiyas.com/inventor/stefan-graef

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 25

% Patents Active = 80.0

Average Co-Inventor Count = 1.7

ph-index = 10

Forward Citations = 394(Granted Patents)

Location History:

San Jose, CA (US) (2003)
Milpitas, CA (US) (1998 - 2011)

Company Filing History:

21 out of 3,715

Lsi Logic Corporation

Years Active: 1998-2011

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Areas of Expertise:

Probe Card Design

Electronic Design Automation

Static Timing Analysis

Integrated Circuit

Circuit Modeling

Delay Estimation

Clock Distribution

Semiconductor Testing

Signal Buffering

Current Analysis

Bus Short Detection

Failure Analysis

25 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 7930219 - Method and system for designing a probe card (2011-04-19),

2. 7593872 - Method and system for designing a probe card (2009-09-22),

3. 7092902 - Automated system for designing and testing a probe card (2006-08-15),

4. 6766499 - Buffer cell insertion and electronic design automation (2004-07-20),

5. 6714828 - Method and system for designing a probe card (2004-03-30),

6. 6687661 - Utilizing a technology-independent system description incorporating a metal layer dependent attribute (2004-02-03),

7. 6634014 - Delay/load estimation for use in integrated circuit design (2003-10-14),

8. 6598213 - Static timing analysis validation tool for ASIC cores (2003-07-22),

9. 6546538 - Integrated circuit having on-chip capacitors for supplying power to portions of the circuit requiring high-transient peak power (2003-04-08),

10. 6532576 - Cell interconnect delay library for integrated circuit design (2003-03-11),

11. 6502230 - Circuit modeling (2002-12-31),

12. 6457160 - Iterative prediction of circuit delays (2002-09-24),

13. 6305001 - Clock distribution network planning and method therefor (2001-10-16),

14. 6189131 - Method of selecting and synthesizing metal interconnect wires in integrated circuits (2001-02-13),

15. 6184711 - Low impact signal buffering in integrated circuits (2001-02-06),

Title: The Innovative Journey of Stefan Graef

Introduction: Stefan Graef is a renowned inventor based in Milpitas, CA (US) known for his groundbreaking contributions to various technological fields.

Latest Patents: Stefan Graef holds several patents in the areas of renewable energy, artificial intelligence, and medical devices, showcasing his diverse range of expertise.

Career Highlights: With a career spanning over two decades, Stefan Graef has worked with leading tech companies, research institutions, and universities to develop cutting-edge solutions that have revolutionized industries.

Collaborations: Throughout his career, Stefan Graef has collaborated with top engineers, scientists, and designers, fostering a culture of innovation and excellence in all his projects.

Conclusion: Stefan Graef's passion for innovation and his relentless pursuit of excellence continue to inspire the next generation of inventors and shape the future of technology.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]