Method of selecting and synthesizing metal interconnect wires in integrated circuits

Abstract

A method for assigning signals to specific metal layers through the use of interconnect wire load models that are metal layer dependent. The method allows synthesis and layout tools to route signal wires on select metal layers at an early stage in the design process. A technology library for use in designing integrated circuits is provided. In addition to traditional library components such as logic gate information, the technology library includes routing wire load models that are metal layer dependent. The wire load information reflects the electrical properties of signal wires formed on different metal layers, and provides more accurate timing estimates than generic wire delay values. The additional information influences the delay calculations of the synthesis process in such a way that the delay a signal encounters on a specific metal layer can be approximated very closely. Of significance to the present invention, a wire-metal layer attribute file is compiled by the synthesis process. The wire-metal layer attribute file output directs layout tools to route individual signals on specific metal layers. Alternatively, the layout tool can utilize the wire-metal layer attribute file to determine a set of acceptable routing layers, allowing an optimal route for a signal to be chosen in relation to the requirements of other signals.