The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2003
Filed:
Dec. 12, 2000
Grant Lindberg, Pleasanton, CA (US);
Stefan Graef, Milpitas, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
Delay and/or load estimation is performed prior to physical layout in an integrated circuit (IC) design process. Initially, a description of the IC design is obtained, the description being in a hardware description language (HDL). Floor planning is then performed based on the HDL description, and buffers are inserted into the IC design based on such floor planning. Finally, delays and/or loads are estimated in the IC design while taking into account the effect of the buffers. The buffers are inserted in the foregoing processing based on anticipated processing later in the IC design process.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile