The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2002
Filed:
May. 02, 2001
Applicant:
Inventors:
Stefan Graef, Milpitas, CA (US);
Sheela Shreedharan, Milpitas, CA (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
The present invention is directed to a system and method of modeling electrical circuits. The present invention may provide improved software for predicting microchip interconnect delays, and in general for an improved semiconductor manufacturing models. Further, the invention may provide for accurate prediction of resistance, capacitance and inductance for interconnections in a semiconductor, allowing for both environmental values and process variations.
Graef, Stefan. (2002). Circuit modeling (U.S. Patent No. 6502230). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6502230
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile