The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2001
Filed:
Jun. 18, 1998
Stefan Graef, Milpitas, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method for planning the clock distribution network in the conceptual design phase of an ASIC device is provided herein that comprises partitioning the technology-independent description of the device into partitioned groups based on the clocking time of the clock recipients in each of the partitioned groups. In addition, a clock budgeting plan is generated by creating target timing groups and assigning each of the partitioned groups to one of the target timing groups based on the clocking time of the clock recipients in each of the partitioned groups. The clock recipients in each of the target timing groups clock at a substantially same time and clock recipients in different target groups clock at different times. The clock distribution network is created based on the clock budgeting plan such that the clock distribution network provides a clock signal to clock recipients in each of the target timing groups in a manner that the clock recipients in each of the target timing groups are clocked together at a substantially same time.