Lsi Logic Corporation

Formfactor, Inc.

Stefan Graef

Emery O Sugasawara

Benjamin N Eldridge

Yves Parent

Mark W Brandemuehl

Juergen K Lahner

Benjamin Mbouombouo

Grant A Lindberg

Oscar M Siguenza

Ludger F Johanterwage

Sheela R Shreedharan

Shalini Rubdi

Floyd Kendrick

Quang Phan

A method and system for designing a probe card from data provided by prospective customers via the Internet is provided. Design specifications are entered into the system by prospective customers and compiled into a database. The collective feasibility of each set of design specifications is determined by an automated computer system and communicated to the prospective customer. If feasible, additional software enables prospective customers to create verification packages according to their respective design specifications. These verification packages further consist of drawing files visually describing the final design and verification files confirming wafer bonding pad data. Verification packages are reviewed and forwarded to an applications engineer after customer approval. An interactive simulation of probe card performance is also provided. Data on probe card performance is incorporated into an overall modeling exercise, which includes not only the probe card, but data on the device(s) under test and wafer, as well as data on automated test equipment.

Method and system for designing a probe card

Automated system for designing and testing a probe card

A computer readable medium encoded with instructions for executing the steps of: receiving information about a driving cell from a layout tool, receiving information about an interconnect from a layout tool, determining buffer cell information based upon information about the driving cell and the interconnect by accessing a previously defined library lookup table, relaying the buffer cell information from the library look up table to the layout tool.

Buffer cell insertion and electronic design automation

When designing an electronic circuit to be implemented on an integrated circuit die which includes several metal layers, a technology-independent description of a system is generated, the technology-independent description specifying a signal and a selected metal layer for the signal. Also, an electronic circuit description of a system is synthesized from a technology-independent description of the system. Specifically, a technology-independent description of the system is input, the technology-independent description specifying a signal and a metal layer attribute for the signal. Electronic components are selected from a library based on the technology-independent description and interconnections between the electronic components are specified. A metal layer is then specified for an interconnection corresponding to the signal specified in the technology-independent description based on the metal layer attribute specified in the technology-independent description.

Utilizing a technology-independent system description incorporating a metal layer dependent attribute

Delay and/or load estimation is performed prior to physical layout in an integrated circuit (IC) design process. Initially, a description of the IC design is obtained, the description being in a hardware description language (HDL). Floor planning is then performed based on the HDL description, and buffers are inserted into the IC design based on such floor planning. Finally, delays and/or loads are estimated in the IC design while taking into account the effect of the buffers. The buffers are inserted in the foregoing processing based on anticipated processing later in the IC design process.

Delay/load estimation for use in integrated circuit design

A method of characterizing worst case timing performance includes the steps of receiving as input a netlist of a core, performing a parasitic extraction on the netlist to generate a first standard parasitic extraction format file for a first assumed top metal layer over the core, performing a parasitic extraction on the netlist to generate a second standard parasitic extraction format file for a second assumed top metal layer over the core, calculating a minimum timing value from each delay arc of the first standard parasitic extraction format file, calculating a maximum timing value from each delay arc of the second standard parasitic extraction format file, and merging the minimum timing value calculated from each delay arc of the first standard parasitic extraction format file and the maximum timing value of each delay arc calculated from the second standard parasitic extraction format file to generate an output file.

Static timing analysis validation tool for ASIC cores

Provided is an integrated circuit (IC) device that includes a semiconductor substrate on which electronic components are formed and multiple metal layers on which wires are routed. Formed on the multiple metal layers is a capacitor that includes a first plate formed on a first metal layer and a second plate formed on a second metal layer that is adjacent to the first metal layer. An area in which the first plate and the second plate overlap has a width of at least twice the width of a typical wire on the IC device. Also provided is a technique for supplying power and ground to locations on an integrated circuit (IC) device that has multiple metal layers for routing wires and a substrate for forming electronic components. Initially, the technique identifies an overlap area where two of the multiple metal layers that are adjacent to each other have open space. A plate is then formed in the overlap area of each of the two metal layers so as to construct a capacitor. Then, one plate of the capacitor is connected to power, the other plate of the capacitor is connected to ground, and the plates of the capacitor are also connected to locations on the substrate of the IC device.

Integrated circuit having on-chip capacitors for supplying power to portions of the circuit requiring high-transient peak power

A method for characterizing cell interconnect delay is disclosed that may be included in a library for use with logic design tools. A method of characterizing cell interconnect delay includes the steps of (a) receiving as inputs a plurality of input ramptimes and a plurality of interconnect lengths for a selected cell, and (b) calculating an output ramptime and a total cell delay including a cell delay and an interconnect delay for each of the plurality of input ramptimes for each of the plurality of interconnect lengths for the selected cell from the inputs.

Cell interconnect delay library for integrated circuit design

The present invention is directed to a system and method of modeling electrical circuits. The present invention may provide improved software for predicting microchip interconnect delays, and in general for an improved semiconductor manufacturing models. Further, the invention may provide for accurate prediction of resistance, capacitance and inductance for interconnections in a semiconductor, allowing for both environmental values and process variations.

Circuit modeling

Provided is a technique for circuit delay prediction in which blocks (preferably, non-overlapping blocks) are specified, each of the blocks including a portion of the circuit. Delay calculation collars (DCCs) are then defined for the blocks, the DCCs including complete dependency information required to calculate delay within the blocks. Next, delay is calculated for the blocks based on the DCCs and delay is calculated for the circuit based on the DCCs. The DCCs are then modified as necessary based on results of either or both of the delay calculation for the blocks or the circuit. The delay calculation and DCC modification steps are then repeated.

Iterative prediction of circuit delays

A method for planning the clock distribution network in the conceptual design phase of an ASIC device is provided herein that comprises partitioning the technology-independent description of the device into partitioned groups based on the clocking time of the clock recipients in each of the partitioned groups. In addition, a clock budgeting plan is generated by creating target timing groups and assigning each of the partitioned groups to one of the target timing groups based on the clocking time of the clock recipients in each of the partitioned groups. The clock recipients in each of the target timing groups clock at a substantially same time and clock recipients in different target groups clock at different times. The clock distribution network is created based on the clock budgeting plan such that the clock distribution network provides a clock signal to clock recipients in each of the target timing groups in a manner that the clock recipients in each of the target timing groups are clocked together at a substantially same time.

Clock distribution network planning and method therefor

A method for assigning signals to specific metal layers through the use of interconnect wire load models that are metal layer dependent. The method allows synthesis and layout tools to route signal wires on select metal layers at an early stage in the design process. A technology library for use in designing integrated circuits is provided. In addition to traditional library components such as logic gate information, the technology library includes routing wire load models that are metal layer dependent. The wire load information reflects the electrical properties of signal wires formed on different metal layers, and provides more accurate timing estimates than generic wire delay values. The additional information influences the delay calculations of the synthesis process in such a way that the delay a signal encounters on a specific metal layer can be approximated very closely. Of significance to the present invention, a wire-metal layer attribute file is compiled by the synthesis process. The wire-metal layer attribute file output directs layout tools to route individual signals on specific metal layers. Alternatively, the layout tool can utilize the wire-metal layer attribute file to determine a set of acceptable routing layers, allowing an optimal route for a signal to be chosen in relation to the requirements of other signals.

Method of selecting and synthesizing metal interconnect wires in integrated circuits

A low impact buffer structure disposed in unused silicon area in a signal line routing channel between logic cell rows of an integrated circuit. In a buffer cell according to the invention, power to the buffer is provided by the power supply rails of one or more nearby logic cell rows. Both the connections to the supply rails and the connections between the transistors of the buffer cell are constructed of a polysilicon material and/or lower metal layer. In this manner, the buffer cell does not significantly impact the routing of metal signal lines in the signal line routing channel. In addition, the buffer cells can be arranged in a &ldquo;staggered&rdquo; configuration wherein separate buffers are provided in individual routing tracks of a signal line routing channel, further reducing the possibility of interference with normal signal routing. In addition, layout and routing tools according to the present invention are capable of monitoring the routing or loading of a signal line to determine when it reaches a length or load factor that may give rise to timing problems. When such a signal line is identified, the routing tool routes the signal line to the nearest available buffer cell or causes a buffer cell to be placed in a convenient location, preferably in the current routing channel. Following the routing process, updated netlist and timing information is generated for back-annotation to other design tools.

Growing community of inventors

Milpitas, CA, United States of America

Stefan Graef