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For the Inventor, By the Inventor

San Jose, CA, United States of America

Shivananda Shetty

This inventor holds 20 USPTO granted patents and 6 published patent applications, primarily in Non-Volatile Memory. Top assignees: Cypress Semiconductor Corporation, Infineon Technologies LLC, Spansion LLC.. Active years: 2014-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shivananda Shetty. Retrieved from https://idiyas.com/inventor/shivananda-shetty

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 20 

% Patents Active = 100.0

Average Co-Inventor Count = 4.7

ph-index = 3

Forward Citations = 20(Granted Patents)


Company Filing History:

goldMedal10 out of 3,598 
 
Cypress Semiconductor Corporation
 patents
silverMedal8 out of 117 
 
Infineon Technologies LLC
 patents
bronzeMedal2 out of 1,075 
 
Spansion LLC.
 patents

Years Active: 2014-2025

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Areas of Expertise:
Data Loss Protection
Non-Volatile Memory
Memory Location Mapping
Dynamic Sensing Levels
Charge Loss Reduction
Program Disturb Suppression
Flash Memory
Memory Device
Gate Height Equalization
Erase Power Loss Indicator
Memory Array
Soft Programming
20 patents (USPTO):Explore Patents
1. 12481578 - Data loss protection for memory systems and devices (2025-11-25),
2. 12444446 - Dynamic sensing levels for nonvolatile memory devices (2025-10-14),
3. 12406747 - Memory location mapping and unmapping (2025-09-02),
4. 12250815 - Methods of equalizing gate heights in embedded non-volatile memory on HKMG technology (2025-03-11),
5. 12131055 - Continuous monotonic counter for memory devices (2024-10-29),
6. 11978528 - Dynamic sensing levels for nonvolatile memory devices (2024-05-07),
7. 11935603 - Erase power loss indicator (EPLI) implementation in flash memory device (2024-03-19),
8. 11567691 - Continuous monotonic counter for memory devices (2023-01-31),
9. 11081194 - Suppression of program disturb with bit line and select gate voltage regulation (2021-08-03),
10. 10957703 - Method of reducing charge loss in non-volatile memories (2021-03-23),
11. 10685724 - Suppression of program disturb with bit line and select gate voltage regulation (2020-06-16),
12. 10679712 - Non-volatile memory device and method of blank check (2020-06-09),
13. 10446245 - Non-volatile memory array with memory gate line and source line scrambling (2019-10-15),
14. 10229745 - Suppression of program disturb with bit line and select gate voltage regulation (2019-03-12),
15. 10192627 - Non-volatile memory array with memory gate line and source line scrambling (2019-01-29),

Title: The Innovative Journey of Inventor Shivananda Shetty

Introduction: Shivananda Shetty, a talented inventor based in San Jose, CA, has made significant contributions to the field of technology with his creative solutions and groundbreaking ideas.

Latest Patents: Shetty holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies, showcasing his versatility and forward-thinking approach to innovation.

Career Highlights: With a background in engineering and a passion for problem-solving, Shetty has successfully developed and implemented various cutting-edge inventions that have had a positive impact on industries ranging from healthcare to sustainable energy.

Collaborations: Throughout his career, Shetty has collaborated with leading research institutions, universities, and tech companies to further his inventions and bring them to market, demonstrating his ability to work effectively in multidisciplinary teams.

Conclusion: Shivananda Shetty's dedication to innovation and his commitment to pushing the boundaries of technology make him a standout figure in the world of inventors, inspiring the next generation of innovators to think outside the box and create solutions that can change the world.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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