The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2024

Filed:

Jan. 11, 2022
Applicant:

Infineon Technologies Llc, San Jose, CA (US);

Inventors:

Amichai Givant, Rosh Ha'Ayin, IL;

Idan Koren, Kiryat Ono, IL;

Shivananda Shetty, San Jose, CA (US);

Pawan Singh, San Jose, CA (US);

Yoram Betser, Mazkeret Batya, IL;

Kobi Danon, Te-Aviv, IL;

Amir Rochman, Tel-aviv, IL;

Assignee:

Infineon Technologies LLC, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/344 (2013.01); G11C 16/0425 (2013.01); G11C 16/0466 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01);
Abstract

A non-volatile memory has an array of non-volatile memory cells, first reference word lines and second reference word lines, and sense amplifiers. The sense amplifiers read system data, that has been written to supplemental non-volatile memory cells of the first reference word lines, using comparison of the supplemental non-volatile memory cells of the first reference word lines to supplemental non-volatile memory cells of the second reference word lines. Status of erasure of the non-volatile memory cells of the array is determined based on reading the system data.


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