The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2020
Filed:
Dec. 04, 2018
Cypress Semiconductor Corporation, San Jose, CA (US);
James Pak, Sunnyvale, CA (US);
Shivananda Shetty, San Jose, CA (US);
Yoram Betser, Mazkeret Batya, IL;
Amichai Givant, Rosh Ha'Ayin, IL;
Jonas Neo, San Jose, CA (US);
Pawan Singh, Santa Clara, CA (US);
Stefano Amato, San Jose, CA (US);
Cindy Sun, Fremont, CA (US);
Amir Rochman, San Jose, CA (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A non-volatile memory device and methods for operating the same are provided. The memory device may have multiple complementary memory cells. The method of blank check includes detecting a state value of each of the true and complementary transistors, generating an upper state value, Wherein a first predetermined amount of the true and complementary transistors have greater state values than the upper state value, generating a lower state value, wherein a second predetermined amount of the true and complementary transistors have less state values than the lower state value, generating a state value range based on a difference between the upper state value and the lower state value, and comparing the state value range to a threshold value to determine whether the plurality of complementary memory cells is in a blank state or a non-blank state. Other embodiments are also disclosed herein.